Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (Asian Test Symposium, 1997)

SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (Asian Test Symposium, 1998)

Novel Technique for Testing FPGAs. - Cecilia Metra; Michel Renovell; Giovanni A. Mojoli; Jean-Michel Portal; Sandro Pastore; Joan Figueras; Yervant Zorian; Davide Salvi; Giacomo R. Sechi (DATE, 1998)

RAM-Based FPGA's: A Test Approach for the Configurable Logic. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (DATE, 1998)

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (FPL, 1998)

SRAM-based FPGA's: testing the LUT/RAM modules. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (ITC, 1998)

Testing the Interconnect of RAM-Based FPGAs. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (IEEE Des. Test Comput., 1998)

Minimizing the Number of Test Configurations for Different FPGA Families. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (Asian Test Symposium, 1999)

Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (DATE, 1999)

Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (ETW, 1999)

SRAM-Based FPGAs: Testing the Embedded RAM Modules. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (J. Electron. Test., 1999)

TOF: a tool for test pattern generation optimization of an FPGA application oriented test. - Michel Renovell; Jean-Michel Portal; Penelope Faure; Joan Figueras; Yervant Zorian (Asian Test Symposium, 2000)

Analyzing the test generation problem for an application-oriented test of FPGAs. - Michel Renovell; Jean-Michel Portal; Penelope Faure; Joan Figueras; Yervant Zorian (ETW, 2000)

Test Configuration Generation for FPGA Logic Cells. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (LATW, 2000)

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. - Michel Renovell; Jean-Michel Portal; Penelope Faure; Joan Figueras; Yervant Zorian (SBCCI, 2000)

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (J. Electron. Test., 2000)

Testing the Local Interconnect Resources of SRAM-Based FPGA's. - Michel Renovell; Jean-Michel Portal; Joan Figueras; Yervant Zorian (J. Electron. Test., 2000)

Analyzing bridging faults impact on EEPROM cell array. - Jean-Michel Portal; Annie Pérez (ETW, 2001)

IS-FPGA : a new symmetric FPGA architecture with implicit scan. - Michel Renovell; Penelope Faure; Jean-Michel Portal; Joan Figueras; Yervant Zorian (ITC, 2001)

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. - Michel Renovell; Jean-Michel Portal; Penelope Faure; Joan Figueras; Yervant Zorian (J. Electron. Test., 2001)

Floating-gate EEPROM cell: threshold voltage sensibility to geometry. - Jean-Michel Portal; L. Forli; Didier Née (ISCAS (1), 2002)

Floating-gate EEPROM cell model based on MOS model 9. - Jean-Michel Portal; L. Forli; Didier Née (ISCAS (3), 2002)

An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. - Jean-Michel Portal; L. Forli; Hassen Aziza; Didier Née (ITC, 2002)

An Automated Design Methodology for EEPROM Cell (ADE). - Jean-Michel Portal; L. Forli; Hassen Aziza; Didier Née (MTDT, 2002)

Infrastructure IP for Back-End Yield Improvement. - L. Forli; Jean-Michel Portal; Didier Née; Bertrand Borot (ITC, 2003)

EEPROM Memory: Threshold Voltage Built In Self Diagnosis. - Jean-Michel Portal; Hassen Aziza; Didier Née (ITC, 2003)

A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. - Sandrine Bernardini; Jean-Michel Portal; Pascal Masson (DATE, 2004)

Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. - Anna Labbé; Annie Pérez; Jean-Michel Portal (ISCAS (2), 2004)

A New Embedded Measurement Structure for eDRAM Capacitor. - Laurent Lopez; Jean-Michel Portal; Didier Née (DATE, 2005)

Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. - B. Saillet; Jean-Michel Portal; Didier Née (DFT, 2005)

EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. - Jean-Michel Portal; Hassen Aziza; Didier Née (J. Electron. Test., 2005)

MM11 based flash memory cell model including characterization procedure. - B. Saillet; Arnaud Régnier; Jean-Michel Portal; B. Delsuc; Romain Laffont; Pascal Masson; Rachid Bouchakour (ISCAS, 2006)

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. - Manuel Sellier; Jean-Michel Portal; Bertrand Borot; Steve Colquhoun; Richard Ferrant; Frédéric Boeuf; Alexis Farcy (ISQED, 2008)

A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. - Olivier Ginez; Jean-Michel Portal; Hassen Aziza (ITC, 2008)

Metal filling impact on standard cells: definition of the metal fill corner concept. - Laurent Remy; Philippe Coll; Fabrice Picot; Philippe Mico; Jean-Michel Portal (SBCCI, 2008)

A Novel Low Power Oriented Design Methodology for Analog Blocks. - Hassen Aziza; Emmanuel Bergeret; Jean-Michel Portal; Olivier Ginez (J. Low Power Electron., 2008)

An on-line testing scheme for repairing purposes in Flash memories. - Olivier Ginez; Jean-Michel Portal; Hassen Aziza (DDECS, 2009)

Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. - Olivier Ginez; Jean-Michel Portal; Christophe Muller (ETS, 2009)

Definition of an innovative filling structure for digital blocks : the DFM filler cell. - Laurent Remy; Philippe Coll; Fabrice Picot; Philippe Mico; Jean-Michel Portal (ICECS, 2009)

Design challenges for prototypical and emerging memory concepts relying on resistance switching. - Christophe Muller; Damien Deleruyelle; Olivier Ginez; Jean-Michel Portal; Marc Bocquet (CICC, 2011)

PSP based DCG-FGT transistor model including characterization procedure. - Abderrezak Marzaki; V. Bidal; Romain Laffont; Wenceslas Rahajandraibe; Jean-Michel Portal; Rachid Bouchakour (ICECS, 2011)

Bipolar OxRRAM memory array reliability evaluation based on fault injection. - Hassen Aziza; Marc Bocquet; Jean-Michel Portal; Christophe Muller (IDT, 2011)

Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area. - Y. Joly; L. Truphemus; Laurent Lopez; Jean-Michel Portal; Hassen Aziza; Franck Julien; Pascal Fornara (ISCAS, 2011)

Analysis of SEU parameters for the study of SRAM cells reliability under radiation. - Karine Castellani-Coulié; Jean-Michel Portal; Gilles Micolau; Hassen Aziza (LATW, 2011)

Impact of SEU configurations on a SRAM cell response at circuit level. - Gilles Micolau; Hassen Aziza; Karine Castellani-Coulié; Jean-Michel Portal (LATW, 2011)

Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. - Santhosh Onkaraiah; Pierre-Emmanuel Gaillardon; Marina Reyboz; Fabien Clermidy; Jean-Michel Portal; Marc Bocquet; Christophe Muller (NANOARCH, 2011)

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress. - Y. Joly; Laurent Lopez; Jean-Michel Portal; Hassen Aziza; Jean-Luc Ogier; Y. Bert; Franck Julien; Pascal Fornara (Microelectron. Reliab., 2011)

Back-end soft and hard defect monitoring using a single test chip. - Fabrice Rigaud; Jean-Michel Portal; Hassen Aziza; Didier Née; Julien Vast; Fabrice Argoud; Bertrand Borot (Microelectron. Reliab., 2011)

PSP based DCG-FGT transistor Model: Full characterization procedure. - Abderrezak Marzaki; V. Bidal; Romain Laffont; Wenceslas Rahajandraibe; Jean-Michel Portal; Rachid Bouchakour (ISCIT, 2012)

Investigation of a CMOS oscillator concept for particle detection and diagnosis. - Karine Castellani-Coulié; Hassen Aziza; Wenceslas Rahajandraibe; Gilles Micolau; Jean-Michel Portal (LATW, 2012)

Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring. - Fayrouz Haddad; Wenceslas Rahajandraibe; Hassen Aziza; Karine Castellani-Coulié; Jean-Michel Portal (LATW, 2012)

SITARe: A simulation tool for analysis and diagnosis of radiation effects. - Gilles Micolau; Karine Castellani-Coulié; Hassen Aziza; Jean-Michel Portal (LATW, 2012)

A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT). - Abderrezak Marzaki; V. Bidal; Romain Laffont; Wenceslas Rahajandraibe; Jean-Michel Portal; Rachid Bouchakour (MWSCAS, 2012)

Crossbar architecture based on 2R complementary resistive switching memory cell. - Weisheng Zhao; Yue Zhang 010; Jacques-Olivier Klein; Damien Querlioz; Djaafar Chabi; Dafine Ravelosona; Claude Chappert; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller (NANOARCH, 2012)

Bipolar ReRAM Based non-volatile flip-flops for low-power architectures. - Santhosh Onkaraiah; Marina Reyboz; Fabien Clermidy; Jean-Michel Portal; Marc Bocquet; Christophe Muller; Hraziia; Costin Anghel; Amara Amara (NEWCAS, 2012)

Optimization of SEU Simulations for SRAM Cells Reliability under Radiation. - Karine Castellani-Coulié; Hassen Aziza; Gilles Micolau; Jean-Michel Portal (J. Electron. Test., 2012)

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. - Guillaume Just; Vincenzo Della Marca; Arnaud Régnier; Jean-Luc Ogier; Jérémy Postel-Pellerin; Jean-Michel Portal; Pascal Masson (J. Low Power Electron., 2012)

Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications. - Jean-Michel Portal; Marc Bocquet; Damien Deleruyelle; Christophe Muller (J. Low Power Electron., 2012)

Low-cost auto-calibration of passive polyphase filter in image reject receiver. - Fayrouz Haddad; Wenceslas Rahajandraibe; Hassen Aziza; Karine Castellani-Coulié; Jean-Michel Portal; Jamel Nebhen; Hervé Barthélemy (ICECS, 2013)

A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. - Santhosh Onkaraiah; Marc Belleville; Marina Reyboz; Fabien Clermidy; Elisa Vianello; Jean-Michel Portal; Christophe Muller (ICICDT, 2013)

Single-ended sense amplifier robustness evaluation for OxRRAM technology. - Hassen Aziza; Marc Bocquet; Mathieu Moreau; Jean-Michel Portal (IDT, 2013)

Embedded high-precision frequency-based capacitor measurement system. - Loic Welter; Philippe Dreux; Jean-Michel Portal; Hassen Aziza (IOLTS, 2013)

A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array. - Santhosh Onkaraiah; Ogun Turkyilmaz; Marina Reyboz; Fabien Clermidy; Elisa Vianello; Jean-Michel Portal; Christophe Muller (ISCAS, 2013)

SPICE level analysis of Single Event Effects in an OxRRAM cell. - Karine Castellani-Coulié; Marc Bocquet; Hassen Aziza; Jean-Michel Portal; Wenceslas Rahajandraibe; Christophe Muller (LATW, 2013)

Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver. - Wenceslas Rahajandraibe; Fayrouz Haddad; Hassen Aziza; Karine Castellani-Coulié; Jean-Michel Portal (LATW, 2013)

DCG-FGT transistor: Retention study of Floating Gate charge. - Abderrezak Marzaki; V. Bidal; Romain Laffont; Wenceslas Rahajandraibe; Jean-Michel Portal; Rachid Bouchakour (MWSCAS, 2013)

Analytical study of complementary memristive synchronous logic gates. - Jean-Michel Portal; Mathieu Moreau; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; et al. (NANOARCH, 2013)

Synchronous full-adder based on complementary resistive switching memory cells. - Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; Weisheng Zhao; Mathieu Moreau; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; et al. (NEWCAS, 2013)

On the investigation of built-in tuning of RF receivers using on-chip polyphase filters. - Fayrouz Haddad; Wenceslas Rahajandraibe; Hassen Aziza; Karine Castellani-Coulié; Jean-Michel Portal (VTS, 2013)

A novel test structure for OxRRAM process variability evaluation. - Hassen Aziza; Marc Bocquet; Jean-Michel Portal; Mathieu Moreau; Christophe Muller (Microelectron. Reliab., 2013)

Resistive memories: Which applications? - Fabien Clermidy; Natalija Jovanovic; Santhosh Onkaraiah; Houcine Oucheikh; Olivier Thomas; Ogun Turkyilmaz; Elisa Vianello; Jean-Michel Portal; Marc Bocquet (DATE, 2014)

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability. - Hassen Aziza; Haithem Ayari; Santhosh Onkaraiah; Jean-Michel Portal; Mathieu Moreau; Marc Bocquet (DFT, 2014)

Accurate multiplexed test structure for threshold voltage matching evaluation. - Loic Welter; Philippe Dreux; Jordan Innocenti; Hassen Aziza; Jean-Michel Portal (DTIS, 2014)

Printed complementary organic thin film transistors based decoder for ferroelectric memory. - Abdelali El Amraoui; Marc Bocquet; F. Barros; Jean-Michel Portal; M. Charbonneau; Stéphanie Jacob; Jacqueline Bablet; Mohamed Benwadih; Vincent Fischer 001; Romain Coppard; R. Gwoziecky (ESSCIRC, 2014)

An innovative standard cells remapping method for in-circuit critical parameters monitoring. - Loic Welter; Philippe Dreux; Hassen Aziza; Jean-Michel Portal (IOLTS, 2014)

Improvement of a VCO concept for low energy particule detection and recognition. - Karine Coulié-Castellani; Wenceslas Rahajandraibe; Gilles Micolau; Hassen Aziza; Jean-Michel Portal (LATW, 2014)

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. - Jordan Innocenti; Loic Welter; Franck Julien; Laurent Lopez; Jacques Sonzogni; Stephan Niel; Arnaud Régnier; Emmanuel Paire; Karen Labory; Eric Denis; Jean-Michel Portal; Pascal Masson (MWSCAS, 2014)

OxRAM-based non volatile flip-flop in 28nm FDSOI. - Nenad Jovanovic; Olivier Thomas; Elisa Vianello; Jean-Michel Portal; Bosko Nikolic; Lirida A. B. Naviner (NEWCAS, 2014)

Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation. - Wenceslas Rahajandraibe; Fayrouz Haddad; Hassen Aziza; Karine Coulié-Castellani; Jean-Michel Portal (J. Low Power Electron., 2014)

RRAM-based FPGA for "Normally Off, Instantly On" applications. - Ogun Turkyilmaz; Santhosh Onkaraiah; Marina Reyboz; Fabien Clermidy; Hraziia; Costin Anghel; Jean-Michel Portal; Marc Bocquet (J. Parallel Distributed Comput., 2014)

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. - Weisheng Zhao; Jean-Michel Portal; Wang Kang 001; Mathieu Moreau; Yue Zhang 010; Hassen Aziza; Jacques-Olivier Klein; Zhaohao Wang; Damien Querlioz; Damien Deleruyelle; Marc Bocquet; Dafine Ravelosona; et al. (J. Parallel Distributed Comput., 2014)

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. - Weisheng Zhao; Mathieu Moreau; Erya Deng; Yue Zhang 010; Jean-Michel Portal; Jacques-Olivier Klein; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Damien Querlioz; Nesrine Ben Romdhane; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment. - Karine Coulié-Castellani; Wenceslas Rahajandraibe; Hassen Aziza; Jean-Michel Portal; Gilles Micolau (LATS, 2015)

Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver. - Wenceslas Rahajandraibe; Fayrouz Haddad; Hassen Aziza; Karine Castellani-Coulié; Jean-Michel Portal (LATS, 2015)

Layout optimizations to decrease internal power and area in digital CMOS standard cells. - Jordan Innocenti; Franck Julien; Jean-Michel Portal; Laurent Lopez; Q. Hubert; Pascal Masson; Jacques Sonzogni; Stephan Niel; Arnaud Régnier (MIPRO, 2015)

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (NVMTS, 2015)

Dynamic current reduction of CMOS digital circuits through design and process optimization. - Jordan Innocenti; Loïc Welter; Nicolas Borrel; Franck Julien; Jean-Michel Portal; Jacques Sonzogni; Laurent Lopez; Pascal Masson; Stephan Niel; Philippe Dreux; Julia Castellan (PATMOS, 2015)

Improvement of MOSFET matching characterization with calibrated multiplexed test structure. - Loic Welter; J. L. Scotto di Quaquero; Philippe Dreux; Laurent Lopez; Hassen Aziza; Jean-Michel Portal (Microelectron. Reliab., 2015)

Multilevel operation in oxide based resistive RAM with SET voltage modulation. - Hassen Aziza; Haithem Ayari; Santhosh Onkaraiah; Mathieu Moreau; Jean-Michel Portal; Marc Bocquet (DTIS, 2016)

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noel; Mathieu Moreau; Jean-Michel Portal (NANOARCH, 2016)

Optimization of a Particles Detection Chain Based on a VCO Structure. - Karine Coulié-Castellani; Wenceslas Rahajandraibe; Gilles Micolau; Hassen Aziza; Jean-Michel Portal (J. Electron. Test., 2016)

Resistive RAM variability monitoring using a ring oscillator based test chip. - Hassen Aziza; Jean-Michel Portal (Microelectron. Reliab., 2016)

Thermal laser attack and high temperature heating on HfO2-based OxRAM cells. - Alexis Krakovinsky; Marc Bocquet; Romain Wacquez; Jean Coignus; Jean-Michel Portal (IOLTS, 2017)

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. - Mahesh Nataraj; Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Pascal Andreas Meinerzhagen; Jean-Michel Portal; Pierre-Emmanuel Gaillardon (ISCAS, 2017)

High density emerging resistive memories: What are the limits? - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (LASCAS, 2017)

Architecture, design and technology guidelines for crosspoint memories. - Alexandre Levisse; Pablo Royer; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (NANOARCH, 2017)

An Ultra-Low Power and High Speed Single Ended Sense Amplifier for Non-Volatile Memories. - Steve Ngueya W.; Julien Mellier; Stephane Ricard; Jean-Michel Portal; Hassen Aziza (NGCAS, 2017)

Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory. - Steve Ngueya W.; Julien Mellier; Stephane Ricard; Jean-Michel Portal; Hassen Aziza (NORCAS, 2017)

High voltage recycling scheme to improve power consumption of regulated charge pumps. - Steve Ngueya W.; Julien Mellier; Stephane Ricard; Jean-Michel Portal; Hassen Aziza (PATMOS, 2017)

A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps. - Steve Ngueya W.; Jean-Michel Portal; Hassen Aziza; Julien Mellier; Stephane Ricard (J. Low Power Electron., 2017)

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (DCIS, 2018)

Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues. - Mounia Kharbouche-Harrari; Jérémy Postel-Pellerin; Gregory di Pendina; Romain Wacquez; Driss Aboulkassimi; Marc Bocquet; R. Sousa; R. Delattre; Jean-Michel Portal (IOLTS, 2018)

Resistive and Spintronic RAMs: Device, Simulation, and Applications. - Elena-Ioana Vatajelu; Lorena Anghel; Jean-Michel Portal; Marc Bocquet; Guillaume Prenat (IOLTS, 2018)

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. - Thibault Kempf; Vincenzo Della Marca; L. Baron; F. Maugain; Francesco La Rosa; Stephan Niel; Arnaud Régnier; Jean-Michel Portal; Pascal Masson (IRPS, 2018)

Reliable ReRAM-based Logic Operations for Computing in Memory. - Mathieu Moreau; Eloi Muhr; Marc Bocquet; Hassen Aziza; Jean-Michel Portal; Bastien Giraud; Jean-Philippe Noel (VLSI-SoC, 2018)

An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories. - Steve Ngueya W.; Jean-Michel Portal; Hassen Aziza; Julien Mellier; Stephane Ricard (J. Low Power Electron., 2018)

Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks. - Tifenn Hirtzlin; Marc Bocquet; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (AICAS, 2019)

Memory-Centric Neuromorphic Computing With Nanodevices. - Damien Querlioz; Julie Grollier; Tifenn Hirtzlin; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Marc Bocquet; Jean-Michel Portal; Miguel Romera; Philippe Talatchian (BioCAS, 2019)

Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM. - Mounia Kharbouche-Harrari; Romain Wacquez; Gregory di Pendina; Jean-Max Dutertre; Jérémy Postel-Pellerin; Driss Aboulkassimi; Jean-Michel Portal (IOLTS, 2019)

Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis. - Mounia Kharbouche-Harrari; Gregory di Pendina; Romain Wacquez; Bernard Dieny; Driss Aboulkassimi; Jérémy Postel-Pellerin; Jean-Michel Portal (ISCAS, 2019)

Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction. - Tifenn Hirtzlin; Bogdan Penkovsky; Jacques-Olivier Klein; Nicolas Locatelli; Adrien F. Vincent; Marc Bocquet; Jean-Michel Portal; Damien Querlioz (NANOARCH, 2019)

Stochastic Computing for Hardware Implementation of Binarized Neural Networks. - Tifenn Hirtzlin; Bogdan Penkovsky; Marc Bocquet; Jacques-Olivier Klein; Jean-Michel Portal; Damien Querlioz (IEEE Access, 2019)

In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks. - Marc Bocquet; Tifenn Hirtzlin; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (CoRR, 2019)

Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays. - Tifenn Hirtzlin; Marc Bocquet; Bogdan Penkovsky; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (CoRR, 2019)

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays. - Mouhamad Alayan; Eloi Muhr; Alexandre Levisse; Marc Bocquet; Mathieu Moreau; Etienne Nowak; Gabriel Molas; Elisa Vianello; Jean-Michel Portal (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse. - Axel Laborieux; Marc Bocquet; Tifenn Hirtzlin; Jacques-Olivier Klein; Liza Herrera Diez; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (AICAS, 2020)

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. - Jean-Philippe Noël; Valentin Egloff; Maha Kooli; Roman Gauchi; Jean-Michel Portal; Henri-Pierre Charles; Pascal Vivet; Bastien Giraud (DATE, 2020)

In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications. - Bogdan Penkovsky; Marc Bocquet; Tifenn Hirtzlin; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (DATE, 2020)

Embracing the Unreliability of Memory Devices for Neuromorphic Computing. - Marc Bocquet; Tifenn Hirtzlin; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (IRPS, 2020)

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. - Alexandre Levisse; Marc Bocquet; Marco Rios; Mouhamad Alayan; Mathieu Moreau; Etienne Nowak; Gabriel Molas; Elisa Vianello; David Atienza; Jean-Michel Portal (IEEE Access, 2020)

Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. - Mona Ezzadeen; D. Bosch; Bastien Giraud; Sylvain Barraud; Jean-Philippe Noël; Didier Lattard; Joris Lacord; Jean-Michel Portal; François Andrieu (CoRR, 2020)

Storage Class Memory with Computing Row Buffer: A Design Space Exploration. - Valentin Egloff; Jean-Philippe Noel; Maha Kooli; Bastien Giraud; Lorenzo Ciampolini; Roman Gauchi; César Fuguet Tortolero; Eric Guthmuller; Mathieu Moreau; Jean-Michel Portal (DATE, 2021)

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. - Mona Ezzadeen; Atreya Majumdar; Marc Bocquet; Bastien Giraud; Jean-Philippe Noël; François Andrieu; Damien Querlioz; Jean-Michel Portal (ESSDERC, 2021)

Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays. - Joel Minguet Lopez; Niccolo Castellani; Laurent Grenouillet; Lucas Reganaz; Gabriele Navarro; Mathieu Bernard; Catherine Carabasse; Thomas Magis; Damien Deleruyelle; Marc Bocquet; Jean-Michel Portal; Etienne Nowak; et al. (IMW, 2021)

Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization. - Joel Minguet Lopez; Lucas Hudeley; Laurent Grenouillet; Diego Alfaro Robayo; Jury Sandrini; Gabriele Navarro; Mathieu Bernard; Catherine Carabasse; Damien Deleruyelle; Niccolo Castellani; Marc Bocquet; Jean-Michel Portal; et al. (IRPS, 2021)

CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks. - Fadi Jebali; Atreya Majumdar; Axel Laborieux; Tifenn Hirtzlin; Elisa Vianello; Jean-Pierre Walder; Marc Bocquet; Damien Querlioz; Jean-Michel Portal (MWSCAS, 2021)

A Self-referenced and regulated sensing solution for PCM with OTS selector. - J. Gasquez; Bastien Giraud; P. Boivin; Y. Moustapha-Rabault; Vincenzo Della Marca; Jean-Pierre Walder; Jean-Michel Portal (VLSI-SoC, 2021)

A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. - J. Gasquez; Bastien Giraud; P. Boivin; Y. Moustapha-Rabault; Vincenzo Della Marca; Jean-Michel Walder; Jean-Michel Portal (VLSI-SoC (Selected Papers), 2021)

Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks. - Atreya Majumdar; Marc Bocquet; Tifenn Hirtzlin; Axel Laborieux; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (CoRR, 2021)

A Memristor-Based Bayesian Machine. - Kamel-Eddine Harabi; Tifenn Hirtzlin; Clement Türck; Elisa Vianello; Raphaël Laurent; Jacques Droulez; Pierre Bessière; Jean-Michel Portal; Marc Bocquet; Damien Querlioz (CoRR, 2021)

Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse. - Axel Laborieux; Marc Bocquet; Tifenn Hirtzlin; Jacques-Olivier Klein; Etienne Nowak; Elisa Vianello; Jean-Michel Portal; Damien Querlioz (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing. - Joel Minguet Lopez; François Rummens; Lucas Reganaz; A. Heraud; Tifenn Hirtzlin; Laurent Grenouillet; Gabriele Navarro; Mathieu Bernard; Catherine Carabasse; Niccolo Castellani; Valentina Meli; S. Martin; et al. (IMW, 2022)

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. - Eduardo Esmanhotto; Tifenn Hirtzlin; Niccolo Castellani; S. Martin; Bastien Giraud; François Andrieu; Jean-François Nodin; Damien Querlioz; Jean-Michel Portal; Elisa Vianello (IRPS, 2022)

Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy. - Eduardo Esmanhotto; Tifenn Hirtzlin; Djohan Bonnet; Niccolo Castellani; Jean-Michel Portal; Damien Querlioz; Elisa Vianello (Adv. Intell. Syst., 2022)

Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential. - Nikhil Garg 002; Ismael Balafrej; Terrence C. Stewart; Jean-Michel Portal; Marc Bocquet; Damien Querlioz; Dominique Drouin; Jean Rouat; Yann Beilliard; Fabien Alibart (CoRR, 2022)

A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. - Kamel-Eddine Harabi; Clement Türck; Marie Drouhin; Adrien Renaudineau; Thomas Bersani-Veroni; Damien Querlioz; Tifenn Hirtzlin; Elisa Vianello; Marc Bocquet; Jean-Michel Portal (ASP-DAC, 2023)

Binary ReRAM-based BNN first-layer implementation. - Mona Ezzadeen; Atreya Majumdar; Sigrid Thomas; Jean-Philippe Noël; Bastien Giraud; Marc Bocquet; François Andrieu; Damien Querlioz; Jean-Michel Portal (DATE, 2023)

Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors. - Clement Türck; Kamel-Eddine Harabi; Tifenn Hirtzlin; Elisa Vianello; Raphaël Laurent; Jacques Droulez; Pierre Bessière; Marc Bocquet; Jean-Michel Portal; Damien Querlioz (DATE, 2023)

1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation. - Joel Minguet Lopez; Manon Dampfhoffer; Tifenn Hirtzlin; Lucas Reganaz; Laurent Grenouillet; Gabriele Navarro; Mathieu Bernard; Thomas Magis; Catherine Carabasse; Niccolo Castellani; Valentina Meli; Elisa Vianello; et al. (MIXDES, 2023)

Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell. - Fadi Jebali; Atreya Majumdar; Clement Türck; Kamel-Eddine Harabi; Mathieu-Coumba Faye; Eloi Muhr; Jean-Pierre Walder; Oleksandr Bilousov; Amadeo Michaud; Elisa Vianello; Tifenn Hirtzlin; François Andrieu; et al. (CoRR, 2023)

Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits. - Nikhil Garg 002; Davide Florini; Patrick Dufour; Eloir Muhr; Mathieu-Coumba Faye; Marc Bocquet; Damien Querlioz; Yann Beilliard; Dominique Drouin; Fabien Alibart; Jean-Michel Portal (ICONS, 2024)

The Logarithmic Memristor-Based Bayesian Machine. - Clement Türck; Kamel-Eddine Harabi; Adrien Pontlevy; Théo Ballet; Tifenn Hirtzlin; Elisa Vianello; Raphaël Laurent; Jacques Droulez; Pierre Bessière; Marc Bocquet; Jean-Michel Portal; Damien Querlioz (CoRR, 2024)

Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits. - Nikhil Garg 002; Davide Florini; Patrick Dufour; Eloi Muhr; Mathieu-Coumba Faye; Marc Bocquet; Damien Querlioz; Yann Beilliard; Dominique Drouin; Fabien Alibart; Jean-Michel Portal (CoRR, 2024)

Dual-Mode 16kb Memory: Transforming a Ferroelectric Capacitor Bitcell into Resistive Filamentary Memory. - Tarcisius Januel; Olivier Billoint; Laurent Grenouillet; S. Martin; Jean-Michel Portal; Elisa Vianello (IMW, 2025)