Full Transceiver Circuit Simulation using VHDL-AMS. - Jean Oudinot; Serge Scotti; Jean Ravatin; Audrey Le-clercq; Jacky Lebrun (ESM, 2002)

Micromotor Simulation with VHDL-AMS. - Jean Oudinot; G. Overton; Aitor Endemaño Isasi; Marc P. Y. Desmulliez; Jean-Yves Fourniols; Sylvaine Muratet (FDL, 2003)

The Most Complete Mixed-Signal Simulation Solution with ADVance MS. - Jean Oudinot (PATMOS, 2003)

VHDL-AMS Library Development for Pacemaker Applications. - B. Hecker; M. Chavassieux; M. Laflutte; E. Beguin; L. Lagasse; Jean Oudinot (DATE, 2004)

SoC modelling for virtual prototyping with VHDL-AMS. - Patricia Desgreys; Yannick Hervé; Jean Oudinot; S. Snaidero; Mohamed Karray (FDL, 2004)

Scalable Model for Multi-Standard Phase Locked Loop. - Benjamin Nicolle; William Tatinian; Jean Oudinot; Gilles Jacquemod (ICECS, 2006)

Hierarchical Modeling of a Fractional Phase Locked Loop. - Benjamin Nicolle; William Tatinian; Jean Oudinot; Gilles Jacquemod (PATMOS, 2006)

Top Verification of Low Power System with "Checkerboard" Approach. - Jean Oudinot (PATMOS, 2006)

Application of Bottom-Up Methodology to RTW VCO. - Fahd Ben Abdeljelil; Benjamin Nicolle; William Tatinian; Lorenzo Carpineto; Jean Oudinot; Gilles Jacquemod (ISVLSI, 2008)