Software environments for computer aided education. - Viviane Guéraud; Jean-Michel Cagnat; Jean-Pierre David; Jean-Philippe Pernin (ACM SIGCSE Bull., 1994)

Hypermedia Exercises Prototyping and Modelising. - Jean-Pierre David; André Cogne; Annick Dutel (CALISCE, 1996)

A Data-Flow Oriented Co-Design for Reconfigurable Systems. - Jean-Pierre David; Jean-Didier Legat (International Workshop on Rapid System Prototyping, 1998)

Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. - Jean-Pierre David; Tony Postiau; Paul Fisette; Jean-Didier Legat (IPDPS, 2001)

An FPGA Implementation of the Linear Cryptanalysis. - François Koeune; Gaël Rouvroy; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Pierre David; Jean-Didier Legat (FPL, 2002)

A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. - Jean-Jacques Quisquater; François-Xavier Standaert; Gaël Rouvroy; Jean-Pierre David; Jean-Didier Legat (FPL, 2002)

An Intermediate Level HDL for System Level Design. - Jean-Pierre David; Etienne Bergeron (FDL, 2004)

A Step towards Intelligent Translation from High-Level Design to RTL. - Jean-Pierre David; Etienne Bergeron (IWSOC, 2004)

High Level Synthesis for Data-Driven Applications. - Etienne Bergeron; Xavier Saint-Mleux; Marc Feeley; Jean-Pierre David (IEEE International Workshop on Rapid System Prototyping, 2005)

Expressing Workshop Scenario with Computer Independent Model. - Jean-Pierre David; Anne Lejeune; Emmanuelle Villiot-Leclercq (ICALT, 2006)

Modeling Collaborative Learning Activities on e-Learning Platforms. - Christian Martel; Laurence Vignollet; Christine Ferraris; Jean-Pierre David; Anne Lejeune (ICALT, 2006)

LDL: An Alternative EML. - Christian Martel; Laurence Vignollet; Christine Ferraris; Jean-Pierre David; Anne Lejeune (ICALT, 2006)

Comparing Educational Modeling Languages on a Case Study. - Laurence Vignollet; Jean-Pierre David; Christine Ferraris; Christian Martel; Anne Lejeune (ICALT, 2006)

Expressing Learning Scenarios with Computer Independent Models. - Emmanuelle Villiot-Leclercq; Jean-Pierre David; Anne Lejeune (ICALT, 2006)

Hardware Complexity of Modular Multiplication and Exponentiation. - Jean-Pierre David; Kassem Kalach; Nicolas Tittley (IEEE Trans. Computers, 2007)

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. - Etienne Bergeron; Marc Feeley; Jean-Pierre David (CC, 2008)

Setting up On-Line Learning Experiments: The LearningLab Platform. - Jean-Michel Adam; Anne Lejeune; Sandra Michelet; Jean-Pierre David; Christian Martel (ICALT, 2008)

Application Specific Instruction set processor specialized for block motion estimation. - Marc-André Daigneault; J. M. Pierre Langlois; Jean-Pierre David (ICCD, 2008)

Analytical model for multi-junction solar cells prediction in space environment. - A. Gauffier; Jean-Pierre David; Olivier Gilard (Microelectron. Reliab., 2008)

A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. - Mathieu Allard; Patrick Grogan; Jean-Pierre David (ReConFig, 2009)

Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. - Tarek Ould Bachir; Jean-Pierre David (FCCM, 2010)

Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). - Marc-André Daigneault; Jean-Pierre David (FPGA, 2010)

A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. - Marc-André Daigneault; Jean-Pierre David (IEEE Trans. Instrum. Meas., 2011)

Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. - Etienne Bergeron; Louis-David Perron; Marc Feeley; Jean-Pierre David (ACM Trans. Reconfigurable Technol. Syst., 2011)

Raising the abstraction level of HDL for control-dominant applications. - Marc-André Daigneault; Jean-Pierre David (FPL, 2012)

Two-level configuration for FPGA: A new design methodology based on a computing fabric. - Mathieu Allard; Patrick Grogan; Yvon Savaria; Jean-Pierre David (ISCAS, 2012)

Effective floating-point calculation engines intended for the FPGA-based HIL simulation. - Tarek Ould-Bachir; Christian Dufour; Jean Bélanger; Jean Mahseredjian; Jean-Pierre David (ISIE, 2012)

Synchronized-transfer-level design methodology applied to hardware matrix multiplication. - Marc-André Daigneault; Jean-Pierre David (ReConFig, 2012)

A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. - Hugo Fortin-Blanchette; Tarek Ould-Bachir; Jean-Pierre David (IEEE Trans. Ind. Electron., 2012)

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. - Marc-André Daigneault; Jean-Pierre David (FCCM, 2013)

Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). - Marc-André Daigneault; Jean-Pierre David (FPGA, 2013)

Max-hashing fragments for large data sets detection. - Jean-Pierre David (ReConFig, 2013)

A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits. - Tarek Ould-Bachir; Christian Dufour; Jean Bélanger; Jean Mahseredjian; Jean-Pierre David (Math. Comput. Simul., 2013)

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. - Tarek Ould-Bachir; Jean-Pierre David (ACM Trans. Reconfigurable Technol. Syst., 2013)

Fast description and synthesis of control-dominant circuits. - Marc-André Daigneault; Jean-Pierre David (Comput. Electr. Eng., 2014)

Mapping applications on two-level configurable hardware. - Himan Khanzadi; Yvon Savaria; Jean-Pierre David (AHS, 2015)

Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver. - Marc-André Daigneault; Jean-Pierre David (IPDPS Workshops, 2015)

BinaryConnect: Training Deep Neural Networks with binary weights during propagations. - Matthieu Courbariaux; Yoshua Bengio; Jean-Pierre David (NIPS, 2015)

Low latency solver for linear equation systems in floating point arithmetic. - Jean-Pierre David (ReConFig, 2015)

Low precision arithmetic for deep learning. - Matthieu Courbariaux; Yoshua Bengio; Jean-Pierre David (ICLR (Workshop), 2015)

A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. - Michel Gemieux; Yvon Savaria; Jean-Pierre David; Guchuan Zhu (ISORC, 2017)

A data driven CGRA Overlay Architecture with embedded processors. - Himan Khanzadi; Yvon Savaria; Jean-Pierre David (NEWCAS, 2017)

Low latency and division free Gauss-Jordan solver in floating point arithmetic. - Jean-Pierre David (J. Parallel Distributed Comput., 2017)

POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. - Ahmed M. Abdelsalam; Ahmed Elsheikh; Jean-Pierre David; J. M. Pierre Langlois (DASIP, 2018)

Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. - Sivakumar Chidambaram; Alexandre Riviello; J. M. Pierre Langlois; Jean-Pierre David (DASIP, 2018)

A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management. - Michel Gemieux; Meng Li 003; Yvon Savaria; Jean-Pierre David; Guchuan Zhu (IEEE Access, 2018)

Ultra-low latency communication channels for FPGA-based HPC cluster. - Roberto Sanchez Correa; Jean-Pierre David (Integr., 2018)

An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. - Federico Montano; Tarek Ould-Bachir; Jean-Pierre David (IEEE Trans. Ind. Electron., 2018)

Automated Synthesis of Streaming Transfer Level Hardware Designs. - Marc-André Daigneault; Jean-Pierre David (ACM Trans. Reconfigurable Technol. Syst., 2018)

A Low-Latency Reconfigurable Multistage Interconnection Network. - Federico Montano; Tarek Ould-Bachir; Jean Mahseredjian; Jean-Pierre David (CCECE, 2019)

POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests. - Ahmed M. Abdelsalam; Ahmed Elsheikh; Jean-Pierre David; J. M. Pierre Langlois (DASIP, 2019)

Binary Speech Features for Keyword Spotting Tasks. - Alexandre Riviello; Jean-Pierre David (INTERSPEECH, 2019)

Bit-Slicing FPGA Accelerator for Quantized Neural Networks. - Olexa Bilaniuk; Sean Wagner; Yvon Savaria; Jean-Pierre David (ISCAS, 2019)

U-Net Fixed-Point Quantization for Medical Image Segmentation. - MohammadHossein AskariHemmat; Sina Honari; Lucas Rouhier; Christian S. Perone; Julien Cohen-Adad; Yvon Savaria; Jean-Pierre David (LABELS/HAL-MICCAI/CuRIOUS@MICCAI, 2019)

On the Use of Interval Arithmetic for the Branch and Bound Delta-Lognormal Parameter Extraction of Rapid Human Movements. - Simon Pierre Boyogueno Bidias; Jean-Pierre David; Yvon Savaria; Réjean Plamondon (The Lognormality Principle, 2020)

RISC-V Barrel Processor for Accelerator Control. - MohammadHossein AskariHemmat; Olexa Bilaniuk; Sean Wagner; Yvon Savaria; Jean-Pierre David (FCCM, 2020)

PoET-BiN: Power Efficient Tiny Binary Neurons. - Sivakumar Chidambaram; Pierre Langlois 001; Jean-Pierre David (MLSys, 2020)

Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. - Aref Trigui; Mohamed Ali 001; Sami Hached; Jean-Pierre David; Ahmed Chiheb Ammari; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst., 2020)

POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. - Ahmed M. Abdelsalam; Ahmed Elsheikh; Sivakumar Chidambaram; Jean-Pierre David; J. M. Pierre Langlois (J. Signal Process. Syst., 2020)

RISC-V Barrel Processor for Deep Neural Network Acceleration. - MohammadHossein AskariHemmat; Olexa Bilaniuk; Sean Wagner; Yvon Savaria; Jean-Pierre David (ISCAS, 2021)

Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. - Jean-Pierre David; Manuel J. Barragán (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. - Mengyue Su; Jean-Pierre David; Yvon Savaria; Bill Pontikakis; Thomas Luinaud (ISCAS, 2022)

Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems. - Jörg Ehmer; Bertrand Granado; Julien Denoulet; Yvon Savaria; Jean-Pierre David (NEWCAS, 2022)

ASIP Accelerator for LUT-based Neural Networks Inference. - Moussa Traore; J. M. Pierre Langlois; Jean-Pierre David (NEWCAS, 2022)

QReg: On Regularization Effects of Quantization. - MohammadHossein AskariHemmat; Reyhane Askari Hemmat; Alexander Hoffman; Ivan Lazarevich; Ehsan Saboori; Olivier Mastropietro; Yvon Savaria; Jean-Pierre David (CoRR, 2022)

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. - Mohammadhossein Askarihemmat; Sean Wagner; Olexa Bilaniuk; Yassine Hariri; Yvon Savaria; Jean-Pierre David (ASP-DAC, 2023)

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. - MohammadHossein AskariHemmat; Théo Dupuis; Yoan Fournier; Nizar El Zarif; Matheus A. Cavalcante; Matteo Perotti; Frank K. Gürkaynak; Luca Benini; François Leduc-Primeau; Yvon Savaria; Jean-Pierre David (ISCAS, 2023)

Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. - Théo Dupuis; Yoan Fournier; MohammadHossein AskariHemmat; Nizar El Zarif; François Leduc-Primeau; Jean-Pierre David; Yvon Savaria (NEWCAS, 2023)

Iterative pruning algorithm for efficient look-up table implementation of binary neural networks. - Amirali Ebrahimi; Vineeth Narayan Pullu; J. M. Pierre Langlois; Jean-Pierre David (NEWCAS, 2023)

Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries. - Dufour Jules; Yvon Savaria; Jean-Pierre David (NEWCAS, 2023)

A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. - Mostafa Elbediwy; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2023)

Training DNNs Resilient to Adversarial and Random Bit-Flips by Learning Quantization Ranges. - Kamran Chitsaz; Gonçalo Mordido; Jean-Pierre David; François Leduc-Primeau (Trans. Mach. Learn. Res., 2023)

Temporal logic explanations for dynamic decision systems using anchors and Monte Carlo Tree Search. - Tzu-Yi Chiu; Jerome Le Ny; Jean-Pierre David (Artif. Intell., 2023)

Temporal Logic Explanations for Dynamic Decision Systems Using Anchors and Monte Carlo Tree Search (Abstract Reprint). - Tzu-Yi Chiu; Jerome Le Ny; Jean-Pierre David (AAAI, 2024)

MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks. - Elisabeth Humblet; Théo Dupuis; Yoan Fournier; MohammadHossein AskariHemmat; François Leduc-Primeau; Jean-Pierre David; Yvon Savaria (MWSCAS, 2024)

Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits. - Aymen-Alaeddine Zeghaida; Dinesh Daultani; J. M. Pierre Langlois; Jean-Pierre David (MWSCAS, 2024)

A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices. - Karim Kaced; Sebastien Genevey; Yvon Savaria; Jean-Pierre David (NewCAS, 2024)

Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. - Nizar El Zarif; MohammadHossein AskariHemmat; Théo Dupuis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2024)

QGen: On the Ability to Generalize in Quantization Aware Training. - MohammadHossein AskariHemmat; Ahmadreza Jeddi; Reyhane Askari Hemmat; Ivan Lazarevich; Alexander Hoffman; Sudhakar Sah; Ehsan Saboori; Yvon Savaria; Jean-Pierre David (CoRR, 2024)

DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. - Mostafa Elbediwy; Bill Pontikakis; Alireza Ghaffari; Jean-Pierre David; Yvon Savaria (IEEE Trans. Netw. Serv. Manag., 2024)

Improved High-Radix Carry-Save Adders for Low-Latency Vector Reduction on Fpga. - Fahimeh Hajizadeh; Paul-André Bisson; Tarek Ould-Bachir; Jean-Pierre David (NewCAS, 2025)

P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. - Mohsen Rahmati; François-Raymond Boyer; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2025)

Enhancing CuFP Library with Self-Alignment Technique. - Fahimeh Hajizadeh; Tarek Ould-Bachir; Jean-Pierre David (Comput., 2025)