Implementation and Performance Evaluation of Bit Manipulation Extension on CVA6 RISC-V. - Muhammad Ijaz; Fatima Saleem; Umer Shahid; Saad Waheed; Jean-Roch Coulon (CF, 2023)

Securing a RISC-V architecture: A dynamic approach. - Sébastien Pillement; Maria Mendez Real; J. Pottier; T. Nieddu; Bertrand Le Gal; Sébastien Faucou; Jean-Luc Béchennec; Mikaël Briday; Sylvain Girbal; Jimmy Le Rhun; Olivier Gilles; Daniel Gracia Pérez; et al. (DATE, 2023)

Using a Performance Model to Implement a Superscalar CVA6. - Côme Allart; Jean-Roch Coulon; André Sintzoff; Olivier Potin; Jean-Baptiste Rigaud (CF (Companion), 2024)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)