High-level synthesis for event-based systems. - Jean Simatic; Rodrigo Possamai Bastos; Laurent Fesquet (EBCCSP, 2016)

New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. - Jean Simatic; Abdelkarim Cherkaoui; Rodrigo Possamai Bastos; Laurent Fesquet (SBCCI, 2016)

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. - Jean Simatic; Abdelkarim Cherkaoui; François Bertrand; Rodrigo Possamai Bastos; Laurent Fesquet (ASYNC, 2017)

High-level synthesis of an event-driven windowing process. - Saeed Mian Qaisar; Jean Simatic; Laurent Fesquet (EBCCSP, 2017)

CAR: On the highway towards de-synchronization. - François Bertrand; Abdelkarim Cherkaoui; Jean Simatic; Anthony Maure; Laurent Fesquet (ICECS, 2017)

Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. - Ali Skaf; Jean Simatic; Laurent Fesquet (ISCAS, 2017)

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. - Assia El-Hadbi; Abdelkarim Cherkaoui; Oussama Elissati; Jean Simatic; Laurent Fesquet (NEWCAS, 2017)

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. - Grégoire Gimenez; Jean Simatic; Laurent Fesquet (ASYNC, 2019)

Comparison of Synchronous and Asynchronous FIR Filter Architectures. - Yoan Decoudu; Jean Simatic; Pauline Alexandre; Katell Morin-Allory; Laurent Fesquet (EBCCSP, 2019)

From High-Level Synthesis to Bundled-Data Circuits. - Yoan Decoudu; Jean Simatic; Katell Morin-Allory; Laurent Fesquet (SAMOS, 2020)