Custom LST chip-set for speech analysis. - P. Zuidweg; Jef L. van Meerbergen; M. L. van der Meulen (ICASSP, 1982)

On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011. - Frans J. van Wijk; Frank P. Welten; Jef L. van Meerbergen; Jan Stoter; Jos A. Huisken; Antoine Delaruelle; Karel E. van Eerdewijk; Josef Schmid; Jan H. Wittek (ICASSP, 1986)

Architectural strategies for an application-specific synchronous multiprocessor environment. - Francky Catthoor; Jan M. Rabaey; Gert Goossens; Jef L. van Meerbergen; Rajeev Jain; Hugo J. De Man; Joos Vandewalle (IEEE Trans. Acoust. Speech Signal Process., 1988)

Definition and assignment of complex data-paths suited for high throughput applications. - Stefaan Note; Francky Catthoor; Jef L. van Meerbergen; Hugo De Man (ICCAD, 1989)

Interprocessor communication in synchronous multiprocessor digital signal processing chips. - Jan Decaluwe; Jan M. Rabaey; Jef L. van Meerbergen; Hugo J. De Man (IEEE Trans. Acoust. Speech Signal Process., 1989)

Synthesis of delay functions in DSP compilers. - Antoine Delaruelle; O. McArdle; Jef L. van Meerbergen; Cees Niessen (EURO-DAC, 1990)

Open-ended system for high-level synthesis of flexible signal processors. - Dirk Lanneer; Francky Catthoor; Gert Goossens; Marc Pauwels; Jef L. van Meerbergen; Hugo De Man (EURO-DAC, 1990)

Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms. - Hugo De Man; Francky Catthoor; Gert Goossens; Jan Vanhoof; Jef L. van Meerbergen; Stefaan Note; Jos A. Huisken (Proc. IEEE, 1990)

An integrated automatic design system for complex DSP algorithms. - Jef L. van Meerbergen; Jos Huisken; Paul E. R. Lippens; O. McArdle; R. Segers; Gert Goossens; Jan Vanhoof; Dirk Lanneer; Francky Catthoor; Hugo De Man (J. VLSI Signal Process., 1990)

PHIDEO: a silicon compiler for high speed algorithms. - Paul E. R. Lippens; Jef L. van Meerbergen; Albert van der Werf; Wim F. J. Verhaegh; B. T. McSweeney; Jos Huisken; O. McArdle (EURO-DAC, 1991)

Hierarchical Retiming Including Pipelining. - Albert van der Werf; B. T. McSweeney; Jef L. van Meerbergen; Paul E. R. Lippens; Wim F. J. Verhaegh (VLSI, 1991)

Efficiency improvements for force-directed scheduling. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jan H. M. Korst; Albert van der Werf; Jef L. van Meerbergen (ICCAD, 1992)

Area optimization of multi-functional processing units. - Albert van der Werf; M. J. H. Peek; Emile H. L. Aarts; Jef L. van Meerbergen; Paul E. R. Lippens; Wim F. J. Verhaegh (ICCAD, 1992)

Consumer applications: a driving force for high-level synthesis of signal-processing architectures. - Rob Woudsma; Jef L. van Meerbergen (IEEE Micro, 1992)

Allocation of multiport memories for hierarchical data stream. - Paul E. R. Lippens; Jef L. van Meerbergen; Wim F. J. Verhaegh; Albert van der Werf (ICCAD, 1993)

A new method for retiming multi-functional processing units. - Albert van der Werf; Emile H. L. Aarts; E. W. Heijnen; Jef L. van Meerbergen; Wim F. J. Verhaegh; Paul E. R. Lippens (VLSI, 1993)

Synthesis of synchronous communication hardware in a multiprocessor architecture. - Jos Huisken; Antoine Delaruelle; B. Egberts; P. Eeckhout; Jef L. van Meerbergen (J. VLSI Signal Process., 1993)

Architectural strategies for high-throughput applications. - Jef L. van Meerbergen; Paul E. R. Lippens; B. T. McSweeney; Wim F. J. Verhaegh; Albert van der Werf; A. van Zanten (J. VLSI Signal Process., 1993)

Optimization of Address Generator Hardware. - Douglas M. Grant; Jef L. van Meerbergen; Paul E. R. Lippens (EDAC-ETC-EUROASIC, 1994)

Efficient timing constraint derivation for optimal retiming high speed processing units. - Albert van der Werf; Jef L. van Meerbergen; Emile H. L. Aarts; Wim F. J. Verhaegh; Paul E. R. Lippens (HLSS, 1994)

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. - Adwin H. Timmer; Marino T. J. Strik; Jef L. van Meerbergen; Jochen A. G. Jess (DAC, 1995)

Analysis and reduction of glitches in synchronous networks. - Jeroen A. J. Leijten; Jef L. van Meerbergen; Jochen A. G. Jess (ED&TC, 1995)

Efficient code generation for in-house DSP-cores. - Marino T. J. Strik; Jef L. van Meerbergen; Adwin H. Timmer; Jochen A. G. Jess; Stefaan Note (ED&TC, 1995)

Improved force-directed scheduling in high-throughput digital signal processing. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jan H. M. Korst; Jef L. van Meerbergen; Albert van der Werf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

PHIDEO: High-level synthesis for high throughput applications. - Jef L. van Meerbergen; Paul E. R. Lippens; Wim F. J. Verhaegh; Albert van der Werf (J. VLSI Signal Process., 1995)

Multidimensional Periodic Scheduling Model and Complexity. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jef L. van Meerbergen; Albert van der Werf (Euro-Par, Vol. II, 1996)

PROPHID: a data-driven multi-processor architecture for high-performance DSP. - Jeroen A. J. Leijten; Jef L. van Meerbergen; Adwin H. Timmer; Jochen A. G. Jess (ED&TC, 1997)

Multidimensional periodic scheduling: a solution approach. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jef L. van Meerbergen (ED&TC, 1997)

PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. - Jeroen A. J. Leijten; Jef L. van Meerbergen; Adwin H. Timmer; Jochen A. G. Jess (ICCD, 1997)

Constraint Analysis for DSP Code Generation. - Bart Mesman; Marino T. J. Strik; Adwin H. Timmer; Jef L. van Meerbergen; Jochen A. G. Jess (ISSS, 1997)

Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. - Jeroen A. J. Leijten; Jef L. van Meerbergen; Adwin H. Timmer; Jochen A. G. Jess (DATE, 1998)

A Constraint Driven Approach to Loop Pipelining and Register Binding. - Bart Mesman; Marino T. J. Strik; Adwin H. Timmer; Jef L. van Meerbergen; Jochen A. G. Jess (DATE, 1998)

The Complexity of Multidimensional Periodic Scheduling. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jef L. van Meerbergen; Albert van der Werf (Discret. Appl. Math., 1998)

Seeking (the right) Problems for the Solutions of Reconfigurable Computing. - Bernardo Kastrup; Jef L. van Meerbergen; Katarzyna Nowak (FPL, 1999)

Constraint analysis for DSP code generation. - Bart Mesman; Adwin H. Timmer; Jef L. van Meerbergen; Jochen A. G. Jess (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A video display processing platform for future TV concepts. - Peter H. N. de With; Egbert G. T. Jaspers; Jef L. van Meerbergen; Adwin H. Timmer; Marino T. J. Strik (IEEE Trans. Consumer Electron., 1999)

Memory Arbitration and Cache Management in Stream-Based Systems. - Françoise Harmsze; Adwin H. Timmer; Jef L. van Meerbergen (DATE, 2000)

Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. - Bernardo Kastrup; Jeroen Trum; Orlando Moreira; Jan Hoogerbrugge; Jef L. van Meerbergen (FPL, 2000)

Prophid: A Platform-Based Design Method. - Jeroen A. J. Leijten; Jef L. van Meerbergen; Adwin H. Timmer; Jochen A. G. Jess (Des. Autom. Embed. Syst., 2000)

Heterogeneous multiprocessor for the management of real-time video and graphics streams. - Marino T. J. Strik; Adwin H. Timmer; Jef L. van Meerbergen; Gert-Jan van Rootselaar (IEEE J. Solid State Circuits, 2000)

Constraint analysis for code generation: basic techniques and applications in FACTS. - Koen van Eijk; Bart Mesman; Carlos A. Alba Pinto; Qin Zhao; Marco Bekooij; Jef L. van Meerbergen; Jochen A. G. Jess (ACM Trans. Design Autom. Electr. Syst., 2000)

Power-efficient layered turbo decoder processor. - John Dielissen; Jef L. van Meerbergen; Marco Bekooij; Françoise Harmsze; Sergej Sawitzki; Jos Huisken; Albert van der Werf (DATE, 2001)

Phase coupled operation assignment for VLIW processors with distributed register files. - Marco Bekooij; Jochen A. G. Jess; Jef L. van Meerbergen (ISSS, 2001)

DF*: Modeling Dynamic Process Creation and Events for Interactive Multimedia Applications. - Sias Mostert; Nathalie Cossement; Rudy Lauwereins; Jef L. van Meerbergen (IEEE International Workshop on Rapid System Prototyping, 2001)

Networks on Silicon: Combining Best-Effort and Guaranteed Services. - Kees Goossens; Paul Wielage; Ad M. G. Peeters; Jef L. van Meerbergen (DATE, 2002)

Embedded Reconfigurable Logic Core for DSP Applications. - Katarzyna Leijten-Nowak; Jef L. van Meerbergen (FPL, 2002)

Guaranteeing the Quality of Services in Networks on Chip. - Kees Goossens; John Dielissen; Jef L. van Meerbergen; Peter Poplavko; Andrei Radulescu; Edwin Rijpkema; Erwin Waterlander; Paul Wielage (Networks on Chip, 2003)

Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. - Peter Poplavko; Twan Basten; Marco Bekooij; Jef L. van Meerbergen; Bart Mesman (CASES, 2003)

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. - Edwin Rijpkema; Kees G. W. Goossens; Andrei Radulescu; John Dielissen; Jef L. van Meerbergen; Paul Wielage; Erwin Waterlander (DATE, 2003)

An FPGA architecture with enhanced datapath functionality. - Katarzyna Leijten-Nowak; Jef L. van Meerbergen (FPGA, 2003)

Towards an efficient high quality picture-rate up-converter. - Aleksandar Beric; Gerard de Haan; Jef L. van Meerbergen; Ramanathan Sethuraman (ICIP (2), 2003)

A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. - Marc Quax; Jos Huisken; Jef L. van Meerbergen (DATE, 2004)

An event-based network-on-chip monitoring service. - Calin Ciordas; Twan Basten; Andrei Radulescu; Kees Goossens; Jef L. van Meerbergen (HLDVT, 2004)

Streaming scratchpad memory organization for video applications. - Aleksandar Beric; Ramanathan Sethuraman; Harm Peters; Gerard Veldman; Jef L. van Meerbergen; Gerard de Haan (Circuits, Signals, and Systems, 2004)

Predictable Embedded Multiprocessor System Design. - Marco Bekooij; Orlando Moreira; Peter Poplavko; Bart Mesman; Milan Pastrnak; Jef L. van Meerbergen (SCOPES, 2004)

A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. - Aleksandar Beric; Ramanathan Sethuraman; Harm Peters; Jef L. van Meerbergen; Gerard de Haan; Carlos A. Alba Pinto (VLSI Design, 2004)

Algorithm/architecture co-design of the generalized sampling theorem based de-interlacer [video signal processing]. - Aleksandar Beric; Gerard de Haan; Jef L. van Meerbergen; Ramanathan Sethuraman (ISCAS (3), 2005)

Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications. - Peter Poplavko; Twan Basten; Milan Pastrnak; Jef L. van Meerbergen; Marco Bekooij; Peter H. N. de With (MEMOCODE, 2005)

Multiprocessor Resource Allocation for Hard-Real-Time Streaming with a Dynamic Job-Mix. - Orlando Moreira; Jan David Mol; Marco Bekooij; Jef L. van Meerbergen (IEEE Real-Time and Embedded Technology and Applications Symposium, 2005)

Performance Guarantees by Simulation of Process Networks. - Marco Bekooij; Jef L. van Meerbergen; Sonali Parma (SCOPES, 2005)

Memory-Centric Motion Estimator. - Aleksandar Beric; Ramanathan Sethuraman; Jef L. van Meerbergen; Gerard de Haan (VLSI Design, 2005)

Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. - Harm Peters; Ramanathan Sethuraman; Aleksandar Beric; Patrick Meuwissen; Srinivasan Balakrishnan; Carlos A. Alba Pinto; W. M. Kruijtzer; Fabian Ernst; Ghiath Alkadi; Jef L. van Meerbergen; Gerard de Haan (IEEE Trans. Circuits Syst. Video Technol., 2005)

An event-based monitoring service for networks on chip. - Calin Ciordas; Twan Basten; Andrei Radulescu; Kees Goossens; Jef L. van Meerbergen (ACM Trans. Design Autom. Electr. Syst., 2005)

An Efficient Picture-Rate Up-Converter. - Aleksandar Beric; Gerard de Haan; Ramanathan Sethuraman; Jef L. van Meerbergen (J. VLSI Signal Process., 2005)

Global Analysis of Resource Arbitration for MPSoC. - Akash Kumar 001; Bart Mesman; Henk Corporaal; Jef L. van Meerbergen; Yajun Ha (DSD, 2006)

Realization of QoS management using negotiation algorithms for multiprocessor NoC. - Milan Pastrnak; Peter H. N. de With; Jef L. van Meerbergen (ISCAS, 2006)

Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. - Chris Bartels; Jos Huisken; Kees Goossens; Patrick Groeneveld; Jef L. van Meerbergen (VLSI-SoC, 2006)

Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies. - Arno Moonen; Chris Bartels; Marco Bekooij; René van den Berg; Harpreet Bhullar; Kees Goossens; Patrick Groeneveld; Jos Huisken; Jef L. van Meerbergen (VLSI-SoC (Selected Papers), 2006)

Qos concept for scalable MPEG-4 video object decoding on multimedia (NoC) chips. - Milan Pastrnak; Peter H. N. de With; Jef L. van Meerbergen (IEEE Trans. Consumer Electron., 2006)

Decoupling of Computation and Communication with a Communication Assist. - Arno Moonen; Marco Bekooij; René van den Berg; Jef L. van Meerbergen (DSD, 2007)

Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism. - Peter Poplavko; Twan Basten; Jef L. van Meerbergen (DSD, 2007)

Ultra Low Power ASIP Design for Wireless Sensor Nodes. - Michael De Nil; Lennart Yseboodt; Frank Bouwens; Jos Hulzink; Mladen Berekovic; Jos Huisken; Jef L. van Meerbergen (ICECS, 2007)

Practical and Accurate Throughput Analysis with the Cyclo Static Dataflow Model. - Arno Moonen; Marco Bekooij; René van den Berg; Jef L. van Meerbergen (MASCOTS, 2007)

Real-time aware rendering of scalable arbitrary-shaped MPEG-4 decoder for multiprocessor systems. - Milan Pastrnak; Peter H. N. de With; Jef L. van Meerbergen (Real-Time Image Processing, 2007)

Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. - Lennart Yseboodt; Michael De Nil; Jos Huisken; Mladen Berekovic; Qin Zhao; Frank Bouwens; Jef L. van Meerbergen (SAMOS, 2007)

Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications. - Marco Bekooij; Maarten Wiggers; Jef L. van Meerbergen (SCOPES, 2007)

Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip. - Arno Moonen; Marco Bekooij; René van den Berg; Jef L. van Meerbergen (DATE, 2008)

Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. - Jochem Govers; Jos Huisken; Mladen Berekovic; Olivier Rousseaux; Frank Bouwens; Michael De Nil; Jef L. van Meerbergen (HiPEAC, 2008)

Memory-Centric Video Processing. - Aleksandar Beric; Jef L. van Meerbergen; Gerard de Haan; Ramanathan Sethuraman (IEEE Trans. Circuits Syst. Video Technol., 2008)

Multi-processor programming in the embedded system curriculum. - Andreas Hansson 001; Benny Akesson; Jef L. van Meerbergen (SIGBED Rev., 2009)

Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. - Lennart Yseboodt; Michael De Nil; Jos Huisken; Mladen Berekovic; Qin Zhao; Frank Bouwens; Jos Hulzink; Jef L. van Meerbergen (J. Signal Process. Syst., 2009)

Low-complexity R-peak detection in ECG signals: A preliminary step towards ambulatory fetal monitoring. - Michiel Rooijakkers; Chiara Rabotti; Martijn Bennebroek; Jef L. van Meerbergen; Massimo Mischi (EMBC, 2011)

A dual-core system solution for wearable health monitors. - Frank Bouwens; Jos Huisken; Harmke de Groot; Martijn Bennebroek; Anteneh A. Abbo; Octavio Santana; Jef L. van Meerbergen; Antoine Fraboulet (ACM Great Lakes Symposium on VLSI, 2011)