Area-oriented iterative method for Design Space Exploration with High-Level Synthesis. - Jeferson Santiago da Silva; Sergio Bampi (LASCAS, 2015)

Extern Objects in P4: an ROHC Compression Case Study. - Jeferson Santiago da Silva; François-Raymond Boyer; Laurent-Olivier Chiquette; J. M. Pierre Langlois (CoRR, 2016)

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. - Jeferson Santiago da Silva; François-Raymond Boyer; J. M. Pierre Langlois (FPGA, 2018)

One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. - Jeferson Santiago da Silva; Thibaut Stimpfling; Thomas Luinaud; Bachir Fradj; Bochra Boughzala (ICNP, 2018)

Extern Objects in P4: an ROHC Header Compression Scheme Case Study. - Jeferson Santiago da Silva; François-Raymond Boyer; Laurent-Olivier Chiquette; J. M. Pierre Langlois (NetSoft, 2018)

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. - Jeferson Santiago da Silva; François-Raymond Boyer; J. M. Pierre Langlois (FCCM, 2019)

Unleashing the Power of FPGAs as Programmable Switches. - Thomas Luinaud; Thibaut Stimpfling; Jeferson Santiago da Silva; Yvon Savaria; J. M. Pierre Langlois (FPGA, 2020)

Bridging the Gap: FPGAs as Programmable Switches. - Thomas Luinaud; Thibaut Stimpfling; Jeferson Santiago da Silva; Yvon Savaria; J. M. Pierre Langlois (HPSR, 2020)

Design Principles for Packet Deparsers on FPGAs. - Thomas Luinaud; Jeferson Santiago da Silva; J. M. Pierre Langlois; Yvon Savaria (FPGA, 2021)