Analysis and representation of composite signals by cepstral inverse filtering. - Jeff H. Derby (ICASSP, 1978)

Comments on "On the design of pole-zero approximations using a logarithmic error measure". - Jeff H. Derby (IEEE Trans. Signal Process., 1996)

High-speed CRC computation using state-space transformations. - Jeff H. Derby (GLOBECOM, 2001)

A high-performance embedded DSP core with novel SIMD features. - Jeff H. Derby; Jaime H. Moreno (ICASSP (2), 2003)

An innovative low-power high-performance programmable signal processor for digital communications. - Jaime H. Moreno; Victor V. Zyuban; Uzi Shvadron; Fredy D. Neeser; Jeff H. Derby; Malcolm S. Ware; Krishnan Kailas; Ayal Zaks; Amir B. Geva; Shay Ben-David; Sameh W. Asaad; Thomas W. Fox; et al. (IBM J. Res. Dev., 2003)

VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. - Jeff H. Derby; Robert K. Montoye; José E. Moreira (Conf. Computing Frontiers, 2006)

Compiling for an indirect vector register architecture. - Dorit Nuzman; Mircea Namolaru; Ayal Zaks; Jeff H. Derby (Conf. Computing Frontiers, 2008)

Performance and power evaluation of an in-line accelerator. - Alejandro Rico; Jeff H. Derby; Robert K. Montoye; Timothy H. Heil; Chen-Yong Cher; Pradip Bose (Conf. Computing Frontiers, 2010)

Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor. - Augusto Vega; Pradip Bose; Alper Buyuktosunoglu; Jeff H. Derby; Michele Franceschini; Charles Johnson; Robert K. Montoye (HPCA, 2012)

Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure. - Dheeraj Sreedhar; Jeff H. Derby; Augusto J. Vega; Brian Rogers; Charles L. Johnson; Robert K. Montoye (ICASSP, 2013)

Matrix-matrix multiplication on a large register file architecture with indirection. - Dheeraj Sreedhar; Jeff H. Derby; Robert K. Montoye; Charles L. Johnson (HiPC, 2014)