An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS. - Jeff L. Sonntag; John T. Stonick; James Gorecki; Bill Beale; Bill Check; Xue-Mei Gong; Joe Guiliano; Kyong Lee; Bob Lefferts; David A. Yokoyama-Martin; Un-Ku Moon; Amber Sengir; et al. (CICC, 2002)

An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS. - John T. Stonick; Gu-Yeon Wei; Jeff L. Sonntag; Daniel Weinlader (IEEE J. Solid State Circuits, 2003)

A new architecture for the fast Viterbi algorithm. - Inkyu Lee; Jeff L. Sonntag (IEEE Trans. Commun., 2003)

A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture. - Kannan Krishna; David A. Yokoyama-Martin; Aaron Caffee; Chris Jones; Mat Loikkanen; James Parker; Ross Segelken; Jeff L. Sonntag; John T. Stonick; Steve Titus; Daniel Weinlader; Skye Wolfer (IEEE J. Solid State Circuits, 2005)

A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS. - David A. Yokoyama-Martin; Kannan Krishna; John T. Stonick; Aaron Caffee; E. K. Gamble; Chris Jones; J. Mcneal; James Parker; Ross Segelken; Jeff L. Sonntag; K. Umino; J. Upton; et al. (CICC, 2006)

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links. - Jeff L. Sonntag; John T. Stonick (IEEE J. Solid State Circuits, 2006)