Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. - Jeffrey T. Draper; Jeff Sondeen; Sumit D. Mediratta; Ihn Kim (ASAP, 2002)

An area-efficient standard-cell floating-point unit design for a processing-in-memory system. - Joong-Seok Moon; Taek-Jun Kwon; Jeff Sondeen; Jeffrey Draper (ESSCIRC, 2003)

A 0.18 µm implementation of a floating-point unit for a processing-in-memory system. - Taek-Jun Kwon; Joong-Seok Moon; Jeff Sondeen; Jeffrey T. Draper (ISCAS (2), 2004)

An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System. - Sumit D. Mediratta; Jeff Sondeen; Jeffrey T. Draper (VLSI Design, 2004)

Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems. - Taek-Jun Kwon; Jeff Sondeen; Jeffrey T. Draper (ISCAS (4), 2005)

An area-efficient and protected network interface for processing-in-memory systems. - Sumit D. Mediratta; Craig S. Steele; Jeff Sondeen; Jeffrey T. Draper (ISCAS (3), 2005)

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. - Jeffrey T. Draper; Tim Barrett; Jeff Sondeen; Sumit D. Mediratta; Chang Woo Kang; Ihn Kim; Gokhan Daglikoca (J. VLSI Signal Process., 2005)

A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability. - Tim Barrett; Sumit D. Mediratta; Taek-Jun Kwon; Ravinder Singh; Sachit Chandra; Jeff Sondeen; Jeffrey T. Draper (ISCAS, 2006)

Floating-point division and square root implementation using a Taylor-series expansion algorithm. - Taek-Jun Kwon; Jeff Sondeen; Jeff Draper (ICECS, 2008)

Multicast routing with dynamic packet fragmentation. - Young Hoon Kang; Jeff Sondeen; Jeffrey T. Draper (ACM Great Lakes Symposium on VLSI, 2009)