Transistor reliability variation correlation to threshold voltage. - Stephen Ramey; M. Chahal; P. Nayak; Steven R. Novak; Chetan Prasad; Jeffery Hicks (IRPS, 2015)

Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology. - F. Griggio; James Palmer 002; F. Pan; N. Toledo; Anthony Schmitz; Ilan Tsameret; R. Kasim; Gerald S. Leatherman; Jeffery Hicks; A. Madhavan; J. Shin; J. Steigerwald; et al. (IRPS, 2018)

Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel's 10+ Process. - Cheyun Lin; Uygar E. Avci; M. A. Blount; Rohit Grover; Jeffery Hicks; R. Kasim; A. Kundu; C. M. Pelto; C. Ryder; Anthony Schmitz; K. Sethi; D. Seghete; et al. (IRPS, 2020)

Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits. - Ketul B. Sutaria; Jihan Standfest; Inanc Meric; Amirhossein H. Davoody; Swaroop Kumar Namalapuri; Trinadh Mutyala; Supriya P.; Balkaran Gill; Stephen Ramey; Jeffery Hicks (IRPS, 2020)

Reliability Modeling of Middle-Of-Line Interconnect Dielectrics in Advanced process nodes. - Rahim Kasim; Cheyun Lin; Christopher Perini; James Palmer 002; N. Gilda; S. Imam; Justin R. Weber; C. Wallace; Jeffery Hicks (IRPS, 2023)

Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing. - Walid M. Hafez; P. Agnihotri; M. Asoro; M. Aykol; B. Bains; Rohan Bambery; M. Bapna; A. Barik; A. Chatterjee; P. C. Chiu; T. Chu; C. Firby; et al. (VLSI Technology and Circuits, 2023)

Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance. - Mauro J. Kobrinsky; J. D. Silva; E. Mannebach; S. Mills; M. Abd El Qader; O. Adebayo; N. Arkali Radhakrishna; M. Beasley; J. Chawla; S. Chugh; A. Dasgupta; U. Desai; et al. (VLSI Technology and Circuits, 2023)

E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. - M. Shamanna; E. Abuayob; G. Aenuganti; C. Alvares; J. Antony; A. Bahudhanam; A. Chandran; P. Chew; A. Chatterjee; B. Chauhan; N. Dandeti; J. Desai; et al. (VLSI Technology and Circuits, 2023)