Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. - Jeffrey B. Goeders; Guy G. F. Lemieux; Steven J. E. Wilton (ReConFig, 2011)

The VTR project: architecture and CAD for FPGAs from verilog to routing. - Jonathan Rose; Jason Luu; Chi Wai Yu; Opal Densmore; Jeffrey Goeders; Andrew Somerville; Kenneth B. Kent; Peter Jamieson; Jason Helge Anderson (FPGA, 2012)

VersaPower: Power estimation for diverse FPGA architectures. - Jeffrey B. Goeders; Steven J. E. Wilton (FPT, 2012)

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. - Eddie Hung; Jeffrey B. Goeders; Steven J. E. Wilton (ARC, 2014)

Effective FPGA debug for high-level synthesis generated circuits. - Jeffrey B. Goeders; Steven J. E. Wilton (FPL, 2014)

Power Aware Architecture Exploration for Field Programmable Gate Arrays. - Jeffrey B. Goeders; Steven J. E. Wilton (J. Low Power Electron., 2014)

VTR 7.0: Next Generation Architecture and CAD System for FPGAs. - Jason Luu; Jeffrey Goeders; Michael Wainberg; Andrew Somerville; Thien Yu; Konstantin Nasartschuk; Miad Nasr; Sen Wang; Tim Liu; Nooruddin Ahmed; Kenneth B. Kent; Jason Helge Anderson; et al. (ACM Trans. Reconfigurable Technol. Syst., 2014)

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. - Jeffrey B. Goeders; Steven J. E. Wilton (FCCM, 2015)

Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. - Jeffrey Goeders; Steven J. E. Wilton (FPT, 2015)

Allowing Software Developers to Debug HLS Hardware. - Jeffrey B. Goeders; Steven J. E. Wilton (CoRR, 2015)

LegUp High-Level Synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Bain Syrowik; Ruolong Lian; Yu Ting Chen; Hsuan Hsiao; Jeffrey B. Goeders; Stephen Brown 003; Jason Helge Anderson (FPGAs for Software Programmers, 2016)

Systems-on-Chip on FPGAs. - Jeffrey B. Goeders; Graham M. Holland; Lesley Shannon; Steven J. E. Wilton (FPGAs for Software Programmers, 2016)

Quantifying observability for in-system debug of high-level synthesis circuits. - Jeffrey Goeders; Steven J. E. Wilton (FPL, 2016)

Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. - Jeffrey Goeders (FCCM, 2017)

Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. - Pavan Kumar Bussa; Jeffrey Goeders; Steven J. E. Wilton (FPL, 2017)

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. - Jeffrey Goeders; Steven J. E. Wilton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. - Jeffrey Goeders; Tanner Gaskin; Brad L. Hutchings (FCCM, 2018)

Architecture Exploration for HLS-Oriented FPGA Debug Overlays. - Al-Shahna Jamal; Jeffrey Goeders; Steven J. E. Wilton (FPGA, 2018)

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. - Al-Shahna Jamal; Jeffrey Goeders; Steven J. E. Wilton (FPL, 2018)

Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs. - Matthew B. Ashcraft; Jeffrey Goeders (FPT, 2018)

Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs. - Adam Hastings; Sean Jensen; Jeffrey Goeders; Brad L. Hutchings (IVSW, 2018)

On-chip FPGA Debug Instrumentation for Machine Learning Applications. - Daniel Holanda Noronha; Ruizhe Zhao; Jeffrey Goeders; Wayne Luk; Steven J. E. Wilton (FPGA, 2019)

Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs. - Matthew B. Ashcraft; Jeffrey Goeders (FPT, 2019)

An Overlay for Rapid FPGA Debug of Machine Learning Applications. - Daniel Holanda Noronha; Ruizhe Zhao; Zhiqiang Que; Jeffrey Goeders; Wayne Luk; Steven J. E. Wilton (FPT, 2019)

Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. - Wesley Stirk; Jeffrey Goeders (ReConFig, 2019)

Using Novel Configuration Techniques for Accelerated FPGA Aging. - Tanner Gaskin; Hayden Cook; Wesley Stirk; Robert Lucas; Jeffrey Goeders; Brad L. Hutchings (FPL, 2020)

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. - Al-Shahna Jamal; Eli Cahill; Jeffrey Goeders; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2020)

Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems. - Benjamin James; Jeffrey Goeders (DATE, 2021)

Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. - Hayden Cook; Jonathan Thompson; Zephram Tripp; Brad L. Hutchings; Jeffrey Goeders (FPT, 2022)

Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering. - Reilly McKendrick; Corey Simpson; Brent Nelson; Jeffrey Goeders (FPT, 2022)

Approaches for FPGA Design Assurance. - Eli Cahill; Brad L. Hutchings; Jeffrey Goeders (ACM Trans. Reconfigurable Technol. Syst., 2022)

Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits. - Hayden Cook; Jacob Arscott; Brent George; Tanner Gaskin; Jeffrey Goeders; Brad L. Hutchings (ACM Trans. Reconfigurable Technol. Syst., 2022)

Improving the Reliability of FPGA CRO PUFs. - Hayden Cook; Zephram Tripp; Brad L. Hutchings; Jeffrey Goeders (FPL, 2023)

Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison. - Reilly McKendrick; Keenan Faulkner; Jeffrey Goeders (ICFPT, 2023)

Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA. - Hayden Cook; Jeffrey Goeders (FPL, 2024)

Open-Source Circuit Radiation Effects (OSCRE) Simulation Framework: Design and Applications. - Collin Lambert; Jacob Anderson; David Nichols; Parker Allred; Sharisse Poff; Jeffrey Goeders; Michael J. Wirthlin; Shiuh-Hua Wood Chiang (ISCAS, 2025)

Toward FPGA Intellectual Property Encryption from Netlist to Bitstream. - Daniel Hutchings; Adam Taylor; Jeffrey Goeders (ACM Trans. Reconfigurable Technol. Syst., 2025)

VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration. - Mohamed A. Elgammal; Amin Mohaghegh; Soheil Gholami Shahrouz; Fatemehsadat Mahmoudi; Fahrican Kosar; Kimia Talaei; Joshua Fife; Daniel Khadivi; Kevin E. Murray; Andrew Boutros; Kenneth B. Kent; Jeffrey B. Goeders; et al. (ACM Trans. Reconfigurable Technol. Syst., 2025)