System design for pixel-parallel image processing. - Jeffrey C. Gealow; Frederick P. Herrmann; L. T. Hsu; Charles G. Sodini (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Invited Address: Integrated Memory/Logic Architecture for Image Processing. - Charles G. Sodini; Jeffrey C. Gealow; Zubair A. Talib; Ichiro Masaki (VLSI Design, 1998)

A pixel-parallel image processor using logic pitch-matched to dynamic memory. - Jeffrey C. Gealow; Charles G. Sodini (IEEE J. Solid State Circuits, 1999)

GSM DAC with new segmented mismatch shaping technique. - Ayman Shabra; Jeffrey C. Gealow; Paul F. Ferguson Jr. (CICC, 2004)

Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits. - Hideyuki Kabuo; Jeffrey C. Gealow (IEEE J. Solid State Circuits, 2014)

Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. - Jeffrey C. Gealow; Masato Motomura (IEEE J. Solid State Circuits, 2015)

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS. - Yunzhi Dong; Jialin Zhao 001; Wenhua Yang 002; Trevor C. Caldwell; Hajime Shibata; Richard Schreier; Qingdong Meng; José B. Silva; Donald Paterson; Jeffrey C. Gealow (ISSCC, 2016)

Foreword. - Jeffrey C. Gealow; Masato Motomura (VLSI Circuits, 2016)

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS. - Yunzhi Dong; Jialin Zhao 001; Wenhua Yang 002; Trevor C. Caldwell; Hajime Shibata; Zhao Li; Richard Schreier; Qingdong Meng; José B. Silva; Donald Paterson; Jeffrey C. Gealow (IEEE J. Solid State Circuits, 2016)

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. - Yunzhi Dong; José B. Silva; Qingdong Meng; Jialin Zhao 001; Wenhua Yang 002; Trevor C. Caldwell; Hajime Shibata; Zhao Li; Donald Paterson; Jeffrey C. Gealow (CICC, 2017)

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Steve Kosic; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; et al. (ISSCC, 2017)

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; Nevena Rakuljic; et al. (IEEE J. Solid State Circuits, 2017)

A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique. - Jialin Zhao 001; Yunzhi Dong; Wenhua Yang 002; Hajime Shibata; Prawal Shrestha; Zhao Li; Trevor C. Caldwell; José B. Silva; Jeffrey C. Gealow (IEEE Trans. Circuits Syst. II Express Briefs, 2018)