Multipurpose DRAM architecture for optimal power, performance, and product flexibility. - Wayne F. Ellis; John E. Barth Jr.; Sri Divakaruni; Jeffrey H. Dreibelbis; Anatol Furman; Erik L. Hedberg; Hsing-San Lee; Thomas M. Maffitt; Christopher P. Miller; Charles H. Stapper; Howard L. Kalter (IBM J. Res. Dev., 1995)

Processor-based built-in self-test for embedded DRAM. - Jeffrey H. Dreibelbis; John Barth 001; Howard L. Kalter; Rex Kho (IEEE J. Solid State Circuits, 1998)

Embedded DRAM built in self test and methodology for test insertion. - Peter Jakobsen; Jeffrey H. Dreibelbis; Gary Pomichter; Darren Anand; John Barth 001; Michael R. Nelms; Jeffrey Leach; George M. Belansek (ITC, 2001)

Test and repair of large embedded DRAMs. I. - Roderick McConnell; Rochit Rajsuman; Eric A. Nelson; Jeffrey H. Dreibelbis (ITC, 2001)

Test and repair of large embedded DRAMs. 2. - Eric A. Nelson; Jeffrey H. Dreibelbis; Roderick McConnell (ITC, 2001)

BIST-Based Bitfail Mapping of an Embedded DRAM. - Brian R. Kessler; Jeffrey H. Dreibelbis; Tim McMahon; Joshua S. McCloy; Rex Kho (MTDT, 2001)

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. - John E. Barth Jr.; Jeffrey H. Dreibelbis; Eric A. Nelson; Darren Anand; Gary Pomichter; Peter Jakobsen; Michael R. Nelms; Jeffrey Leach; George M. Belansek (IBM J. Res. Dev., 2002)

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)