Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. - Jeffrey J. Cook; Derek B. Gottlieb; Joshua D. Walstrom; Steve Ferrera; Chi-Wei Wang; Nicholas P. Carter (FCCM, 2002)

The Design of the Amalgam Reconfigurable Cluster. - Joshua D. Walstrom; Jeffrey J. Cook; Derek B. Gottlieb; Steve Ferrera; Chi-Wei Wang; Nicholas P. Carter (FCCM, 2002)

Clustered programmable-reconfigurable processors. - Derek B. Gottlieb; Jeffrey J. Cook; Joshua D. Walstrom; Steve Ferrera; Chi-Wei Wang; Nicholas P. Carter (FPT, 2002)

Mapping computation kernels to clustered programmable-reconfigurable processors. - Jeffrey J. Cook; Lee Baugh; Derek B. Gottlieb; Nicholas P. Carter (FPT, 2003)

A reconfigurable unit for a clustered programmable-reconfigurable processor. - Richard B. Kujoth; Chi-Wei Wang; Derek B. Gottlieb; Jeffrey J. Cook; Nicholas P. Carter (FPGA, 2004)

Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. - Chi-Wei Wang; Nicholas P. Carter; Richard B. Kujoth; Jeffrey J. Cook; Derek B. Gottlieb (FPL, 2005)

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. - Richard B. Kujoth; Chi-Wei Wang; Jeffrey J. Cook; Derek B. Gottlieb; Nicholas P. Carter (Microprocess. Microsystems, 2007)

A characterization of instruction-level error derating and its implications for error detection. - Jeffrey J. Cook; Craig B. Zilles (DSN, 2008)

Blueshift: Designing processors for timing speculation from the ground up. - Brian Greskamp; Lu Wan; Ulya R. Karpuzcu; Jeffrey J. Cook; Josep Torrellas; Deming Chen; Craig B. Zilles (HPCA, 2009)

Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. - Jeffrey J. Cook; Craig B. Zilles (ISPASS, 2009)

Scaling short read de novo DNA sequence assembly to gigabase genomes - Jeffrey J. Cook (2011)

WRPN: Training and Inference using Wide Reduced-Precision Networks. - Asit K. Mishra; Jeffrey J. Cook; Eriko Nurvitadhi; Debbie Marr (CoRR, 2017)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Sergey Y. Shumarayev; Aravind Dasu (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Aravind Dasu; Sergey Y. Shumarayev (FPL, 2018)

WRPN: Wide Reduced-Precision Networks. - Asit K. Mishra; Eriko Nurvitadhi; Jeffrey J. Cook; Debbie Marr (ICLR (Poster), 2018)