Chameleon: a new multi-layer channel router. - Douglas Braun; Jeffrey L. Burns; Srinivas Devadas; Hi-Keung Tony Ma; Kartikeya Mayaram; Fabio Romeo; Alberto L. Sangiovanni-Vincentelli (DAC, 1986)

Techniques for multilayer channel routing. - Douglas Braun; Jeffrey L. Burns; Fabio Romeo; Alberto L. Sangiovanni-Vincentelli; Kartikeya Mayaram; Srinivas Devadas; Hi-Keung Tony Ma (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

The Effect of Wire Length Minimization on Yield. - Venkat K. R. Chiluvuri; Israel Koren; Jeffrey L. Burns (DFT, 1994)

Area-oriented synthesis for pass-transistor logic. - Rajat Chaudhry; Tai-Hung Liu; Adnan Aziz; Jeffrey L. Burns (ICCD, 1998)

Design methodology for a 1.0 GHz microprocessor. - Stephen D. Posluszny; Naoaki Aoki; David Boerstler; Jeffrey L. Burns; Sang H. Dhong; Uttam Ghoshal; H. Peter Hofstee; David P. LaPotin; Kyung T. Lee; David Meltzer; Hung C. Ngo; Kevin J. Nowka; et al. (ICCD, 1998)

A 1.0-GHz single-issue 64-bit powerPC integer processor. - Joel Silberman; Naoaki Aoki; David Boerstler; Jeffrey L. Burns; Sang H. Dhong; Axel Essbaum; Uttam Ghoshal; David F. Heidel; H. Peter Hofstee; Kyung T. Lee; David Meltzer; Hung C. Ngo; et al. (IEEE J. Solid State Circuits, 1998)

Designing for a gigahertz [guTS integer processor]. - H. Peter Hofstee; Sang H. Dhong; David Meltzer; Kevin J. Nowka; Joel Silberman; Jeffrey L. Burns; Stephen D. Posluszny; Osamu Takahashi (IEEE Micro, 1998)

C5M-a control-logic layout synthesis system for high-performance microprocessors. - Jeffrey L. Burns; Jack A. Feldman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Performance Driven Synthesis for Pass-Transistor Logic. - Tai-Hung Liu; Malay K. Ganai; Adnan Aziz; Jeffrey L. Burns (VLSI Design, 1999)

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. - Kevin J. Nowka; Gary D. Carpenter; Eric W. MacDonald; Hung C. Ngo; Bishop Brock; Koji I. Ishii; Tuyet Nguyen; Jeffrey L. Burns (IEEE J. Solid State Circuits, 2002)

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. - Rahul M. Rao; Jeffrey L. Burns; Richard B. Brown (ESSCIRC, 2003)

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. - Rahul M. Rao; Frank Liu 001; Jeffrey L. Burns; Richard B. Brown (ICCAD, 2003)

Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. - Vikas Chandra; Gary D. Carpenter; Jeffrey L. Burns (ICCD, 2003)

Leakage and leakage sensitivity computation for combinational circuits. - Emrah Acar; Anirudh Devgan; Rahul M. Rao; Ying Liu; Haihua Su; Sani R. Nassif; Jeffrey L. Burns (ISLPED, 2003)

A semi-custom voltage-island technique and its application to high-speed serial links. - Juan Antonio Carballo; Jeffrey L. Burns; Seung-Moon Yoo; Ivan Vo; V. Robert Norman (ISLPED, 2003)

Efficient techniques for gate leakage estimation. - Rahul M. Rao; Jeffrey L. Burns; Anirudh Devgan; Richard B. Brown (ISLPED, 2003)

Analysis and Optimization of Enhanced MTCMOS Scheme. - Rahul M. Rao; Jeffrey L. Burns; Richard B. Brown (VLSI Design, 2004)

Resonant clocking using distributed parasitic capacitance. - Alan J. Drake; Kevin J. Nowka; Tuyet Nguyen; Jeffrey L. Burns; Richard B. Brown (IEEE J. Solid State Circuits, 2004)

Technology trends and implications on SoC design. - Jeffrey L. Burns (SoCC, 2011)

Panel discussions: "Cool chips for the next decade". - Hideharu Amano; Tadao Nakamura; Hiroaki Kobayashi; Hironori Kasahara; Yoshiaki Hagiwara; Jeffrey L. Burns; David Brash (COOL Chips, 2017)