Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. - John M. Ludden; Wolfgang Roesner; Gerry M. Heiling; John R. Reysa; Jonathan R. Jackson; Bing-Lun Chu; Michael L. Behm; Jason Baumgartner; Richard D. Peterson; Jamee Abdulhafiz; William E. Bucy; John H. Klaus; et al. (IBM J. Res. Dev., 2002)

Automatic testcase synthesis and performance model validation for high performance PowerPC processors. - Robert H. Bell Jr.; Rajiv R. Bhatia; Lizy K. John; Jeff Stuecheli; John Griswell; Paul Tu; Louis Capps; Anton Blanchard; Ravel Thai (ISPASS, 2006)

Bank-aware Dynamic Cache Partitioning for Multicore Architectures. - Dimitris Kaseridis; Jeffrey Stuecheli; Lizy K. John (ICPP, 2009)

A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems. - Dimitris Kaseridis; Jeffrey Stuecheli; Jian Chen 030; Lizy Kurian John (HPCA, 2010)

The virtual write queue: coordinating DRAM and last-level cache policies. - Jeffrey Stuecheli; Dimitris Kaseridis; David Daly; Hillery C. Hunter; Lizy K. John (ISCA, 2010)

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. - Jeffrey Stuecheli; Dimitris Kaseridis; Hillery C. Hunter; Lizy K. John (MICRO, 2010)

MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches. - Dimitris Kaseridis; Muhammad Faisal Iqbal; Jeffrey Stuecheli; Lizy Kurian John (PACT, 2011)

Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. - Dimitris Kaseridis; Jeffrey Stuecheli; Lizy Kurian John (MICRO, 2011)

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. - Jeffrey Stuecheli; Dimitris Kaseridis; David Daly; Hillery C. Hunter; Lizy K. John (IEEE Micro, 2011)

POWER8. - Jeff Stuecheli (Hot Chips Symposium, 2013)

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. - Janani Mukundan; Hillery C. Hunter; Kyu-Hyoun Kim; Jeffrey Stuecheli; José F. Martínez (ISCA, 2013)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

Advanced features in IBM POWER8 systems. - Balaram Sinharoy; Randal C. Swanberg; Naresh Nayar; Bruce G. Mealey; Jeffrey Stuecheli; Berni Schiefer; Jens Leenstra; Joefon Jann; P. Oehler; D. Levitan; S. Eisen; D. Sanner; et al. (IBM J. Res. Dev., 2015)

The cache and memory subsystems of the IBM POWER8 processor. - William J. Starke; Jeffrey Stuecheli; David Daly; J. S. Dodson; Florian Auernhammer; Patricia Sagmeister; Guy L. Guthrie; Charles F. Marino; M. S. Siegel; Bart Blaner (IBM J. Res. Dev., 2015)

CAPI: A Coherent Accelerator Processor Interface. - Jeffrey Stuecheli; Bart Blaner; C. R. Johns; M. S. Siegel (IBM J. Res. Dev., 2015)

An Early Performance Study of Large-Scale POWER8 SMP Systems. - Xing Liu; Daniele Buono; Fabio Checconi; Jee W. Choi; Xinyu Que; Fabrizio Petrini; John A. Gunnels; Jeff Stuecheli (IPDPS, 2016)

IBM POWER9 memory architectures for optimized systems. - William J. Starke; J. S. Dodson; Jeffrey Stuecheli; Eric Retter; Brad W. Michael; Stephen J. Powell; James A. Marcella (IBM J. Res. Dev., 2018)

IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. - Jeffrey Stuecheli; William J. Starke; John D. Irish; L. Baba Arimilli; Daniel M. Dreps; Bart Blaner; Curt Wollbrink; Brian Allison (IBM J. Res. Dev., 2018)

IBM's Next Generation POWER Processor. - Jeff Stuecheli; Scott Willenborg; William J. Starke (Hot Chips Symposium, 2019)

Confidential computing for OpenPOWER. - Guerney D. H. Hunt; Ramachandra Pai; Michael V. Le; Hani Jamjoom; Sukadev Bhattiprolu; Rick Boivie; Laurent Dufour; Brad Frey; Mohit Kapur; Kenneth A. Goldman; Ryan Grimm; Janani Janakirman; et al. (EuroSys, 2021)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)

IBM's POWER10 Processor. - William J. Starke; Brian W. Thompto; Jeffrey Stuecheli; José E. Moreira (IEEE Micro, 2021)