A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

An efficient statistical analysis methodology and its application to high-density DRAMs. - Sang-Hoon Lee; Chang-hoon Choi; Jeong-Taek Kong; Wong-Seong Lee; Jei-Hwan Yoo (ICCAD, 1997)

Low-voltage, high-speed circuit designs for gigabit DRAMs. - Kyu-Chan Lee; Changhyun Kim; Dong-Ryul Ryu; Jai-Hoon Sim; Sang-Bo Lee; Byung-Sik Moon; Keum-Yong Kim; Nam-Jong Kim; Seung-Moon Yoo; Hongil Yoon; Jei-Hwan Yoo; Soo-In Cho (IEEE J. Solid State Circuits, 1997)

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. - Jae-Yoon Sim; Hongil Yoon; Ki-Chul Chun; Hyun-Seok Lee; Sang-Pyo Hong; Kyu-Chan Lee; Jei-Hwan Yoo; Dong-Il Seo; Soo-In Cho (IEEE J. Solid State Circuits, 2003)

8Gb 3D DDR3 DRAM using through-silicon-via technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Soon-Hong Ahn; Hoon Lee; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jin Ho Kim; Jae-Wook Lee 007; Han-Sung Joo; Woo-Seop Kim; et al. (ISSCC, 2009)

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. - Young-Chan Jang; Hoeju Chung; Youngdon Choi; Hwan-Wook Park; Jaekwan Kim 003; Soouk Lim; Jung Sunwoo; Moon-Sook Park; Hyung-Seuk Kim; Sang-Yun Kim; Yun-Sang Lee; Woo-Seop Kim; et al. (IEEE J. Solid State Circuits, 2009)

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Dukha Park; Hoon Lee; Jin Ho Kim; Soon-Hong Ahn; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jae-Wook Lee 007; Han-Sung Joo; et al. (IEEE J. Solid State Circuits, 2010)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. - Ki-Whan Song; Jinyoung Kim; Jae-Man Yoon; Sua Kim; Huijung Kim; Hyun-Woo Chung; Hyungi Kim; Kanguk Kim; Hwan-Wook Park; Hyun Chul Kang; Nam-Kyun Tak; Dukha Park; et al. (IEEE J. Solid State Circuits, 2010)

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. - Hoeju Chung; Byung-Hoon Jeong; ByungJun Min; Youngdon Choi; Beak-Hyung Cho; Junho Shin; Jinyoung Kim; Jung Sunwoo; Joon-min Park; Qi Wang; Yong-jun Lee; Sooho Cha; et al. (ISSCC, 2011)

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. - Youngdon Choi; Ickhyun Song; Mu-Hui Park; Hoeju Chung; Sanghoan Chang; Beakhyoung Cho; Jinyoung Kim; Younghoon Oh; Dukmin Kwon; Jung Sunwoo; Junho Shin; Yoohwan Rho; et al. (ISSCC, 2012)