High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. - Hong-Yi Huang; Bo-Ruei Wang; Jen-Chieh Liu (ISCAS, 2006)

All-Digital PLL Using Pulse-Based DCO. - Hong-Yi Huang; Jen-Chieh Liu; Kuo-Hsing Cheng (ICECS, 2007)

0.5V 160-MHz 260uW all digital phase-locked loop. - Jen-Chieh Liu; Hong-Yi Huang; Wei-Bin Yang; Kuo-Hsing Cheng (DDECS, 2009)

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. - Kuo-Hsing Cheng; Chang-Chien Hu; Jen-Chieh Liu; Hong-Yi Huang (DDECS, 2010)

A loading effect insensitive and high precision clock synchronization circuit. - Kai-Wei Hong; Kuo-Hsing Cheng; Chi-Hsiang Chen; Jen-Chieh Liu; Chien-Cheng Chen (ESSCIRC, 2010)

All digital phase-locked loop using active inductor oscillator and novel locking algorithm. - Tzu-Chi Huang; Hong-Yi Huang; Jen-Chieh Liu; Kuo-Hsing Cheng; Ching-Hsing Luo (ISCAS, 2011)

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. - Kuo-Hsing Cheng; Jen-Chieh Liu; Hong-Yi Huang; Yu-Liang Li; Yong-Jhen Jhu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. - Kuo-Hsing Cheng; Kai-Wei Hong; Chi-Hsiang Chen; Jen-Chieh Liu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. - Kuo-Hsing Cheng; Jen-Chieh Liu; Chih-Yu Chang; Shu-Yu Jiang; Kai-Wei Hong (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Auto-calibration techniques in built-in jitter measurement circuit. - Chih-Ping Cheng; Jen-Chieh Liu; Kuo-Hsing Cheng (DDECS, 2012)

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. - Kuo-Hsing Cheng; Jen-Chieh Liu; Hong-Yi Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 64-MHz∼640-MHz 64-phase clock generator. - Hong-Yi Huang; Jen-Chieh Liu; Shi-Jia Sun; Cheng-Hao Fu; Kuo-Hsing Cheng (DDECS, 2014)

A radio-controlled receiver for clocks/watches and alarm applications. - Jen-Chieh Liu; Huan-Ke Chiu; Jia-Hung Peng; Yuan-Hua Chu; Hong-Yi Huang (ISCAS, 2014)

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. - Kuo-Hsing Cheng; Cheng-Liang Hung; Cihun-Siyong Alex Gong; Jen-Chieh Liu; Bo-Qian Jiang; Shi-Yang Sun (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. - Hong-Yi Huang; Jen-Chieh Liu; Pei-Ying Lee; Kun-Yuan Chen; Jin-Sheng Chen; Kuo-Hsing Cheng; Tzuen-Hsi Huang; Ching-Hsing Luo; Jin-Chern Chiou (DDECS, 2015)

A chaotically injected timing technique for ring-based oscillators. - Yo-Hao Tu; Kuo-Hsing Cheng; Wei-Ren Wang; Jen-Chieh Liu; Hong-Yi Huang (DDECS, 2016)

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. - Yo-Hao Tu; Jen-Chieh Liu; Kuo-Hsing Cheng; Hong-Yi Huang; Chang-Chien Hu (IEICE Electron. Express, 2016)

A Low Power Pulse Generator for Test Platform Applications. - Jen-Chieh Liu; Pei-Ying Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. - Yo-Hao Tu; Jen-Chieh Liu; Kuo-Hsing Cheng (IEICE Trans. Electron., 2016)

A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. - Ting-Chou Lu; Ming-Dou Ker; Hsiao-Wen Zan; Jen-Chieh Liu; Yu Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Low supply voltage and multiphase all-digital crystal-less clock generator. - Yo-Hao Tu; Jen-Chieh Liu; Kuo-Hsing Cheng; Chi-Yang Chang (IET Circuits Devices Syst., 2018)

Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design. - Jen-Chieh Liu; Tzu-Yun Wu; Tuo-Hung Hou (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. - Yo-Hao Tu; Kuo-Hsing Cheng; Man-Ju Lee; Jen-Chieh Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution. - Jen-Chieh Liu; Chao-Jen Huang; Pei-Ying Lee (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator. - Jen-Chieh Liu; Yu-Ping Li (IEEE Access, 2021)

A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique. - Hong-Yi Huang; Jen-Chieh Liu; Fu-Chien Tsai; Kun-Hua Lee; Kun-Yuan Chen (Circuits Syst. Signal Process., 2023)

A Low-power PLL with a Standby Mode. - Yu-Chun Hsiao; Rui-Cheng Ai; Zhen-Jie Hong; Yu-Lung Lo; Jen-Chieh Liu (ISOCC, 2024)

A Programmable DLL-based Delay Chain. - Yu-Wei Huang; Cheng-En Wu; Wei-Bin Yang; Jen-Chieh Liu (ISOCC, 2024)

A low-voltage and low-power PLL for Sub-GHz IoT applications. - Jen-Chieh Liu; Rui-Cheng Ai (Integr., 2025)

A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application. - Jen-Chieh Liu; Jian-Sheng Li; Yanxun Chen; Yu-Lung Lo (Microelectron. J., 2025)

A High Timing Resolution and Data Rate Pulse Generator for Automatic Test Equipment Applications. - Jen-Chieh Liu; Chi-Hua Chen; Cheng-En Wu (IEEE Trans. Instrum. Meas., 2025)