An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding. - Yeong-Luh Ueng; Bo-Jhang Yang; Chung-Jay Yang; Huang-Chang Lee; Jeng-Da Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. - Chung-Chao Cheng; Jeng-Da Yang; Huang-Chang Lee; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)