Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology. - Ming-Dou Ker; Jeng-Jie Peng (CICC, 1998)

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. - Ming-Dou Ker; Hsin-Chin Jiang; Jeng-Jie Peng; Tzay-Luen Shieh (ICECS, 2001)

ESD test methods on integrated circuits: an overview. - Ming-Dou Ker; Jeng-Jie Peng; Hsin-Chin Jiang (ICECS, 2001)

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. - Jeng-Jie Peng; Ming-Dou Ker; Hsin-Chin Jiang (ISCAS (5), 2002)

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. - Ming-Dou Ker; Hsin-Chyh Hsu; Jeng-Jie Peng (ISQED, 2003)

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. - Ming-Dou Ker; Jeng-Jie Peng; Hsin-Chin Jiang (ISQED, 2003)