A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. - Jenlung Liu; Sehyung Jeon; Tae-Kwang Jang; Dohyung Kim; Jihyun F. Kim; Jaejin Park; Hojin Park (A-SSCC, 2011)

A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. - Jong-Phil Hong; Sung-Jin Kim; Jenlung Liu; Nan Xing; Tae-Kwang Jang; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2012)

15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. - Jenlung Liu; Tae-Kwang Jang; Yonghee Lee; Jungeun Shin; Seunghoon Lee; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2014)