Artificial Neural Networks for the Bipartite and K-partite Subgraph Problems. - Jenn-Shiang Lai; Young-Ja Ko; Sy-Yen Kuo (PARLE, 1993)

Neural Networks for Optimization Problems in Graph Theory. - Jenn-Shiang Lai; Sy-Yen Kuo; Ing-Yi Chen (ISCAS, 1994)

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. - Yun-Chao You; Chi-Chun Yang; Jin-Fu Li 001; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (ATS, 2014)

A hybrid built-in self-test scheme for DRAMs. - Chi-Chun Yang; Jin-Fu Li 001; Yun-Chao Yu; Kuan-Te Wu; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2015)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Tah-Kang Joseph Ting; Gyh-Bin Wang; Ming-Hung Wang; Chun-Peng Wu; Chun-Kai Wang; Chun-Wei Lo; Li-Chin Tien; Der-Min Yuan; Yung-Ching Hsieh; Jenn-Shiang Lai; Wen-Pin Hsu; Chien-Chih Huang; et al. (ISSCC, 2017)

Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. - Tsung-Fu Hsieh; Jin-Fu Li 001; Kuan-Te Wu; Jenn-Shiang Lai; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC-Asia, 2017)

A channel-sharable built-in self-test scheme for multi-channel DRAMs. - Kuan-Te Wu; Jin-Fu Li 001; Chih-Yen Lo; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (ASP-DAC, 2018)

Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. - Tsung-Fu Hsieh; Jin-Fu Li 001; Jenn-Shiang Lai; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC-Asia, 2020)