A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture. - Sang Min Lee 014; Dongwon Seo; Shahin Mehdizad Taleie; Derui Kong; Michael Joseph McGowan; Tongyu Song; Ganesh R. Saripalli; Jenny Kuo; Seyfi S. Bazarjani (VLSIC, 2015)

Digital Background Calibration of a Split Current-Steering DAC. - David J. Stoops; Jenny Kuo; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)