Jens Brandt

According to our database1, Jens Brandt authored at least 44 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2017
Quartz: A Synchronous Language for Model-Based Design of Reactive Embedded Systems.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

2014
Passive code in synchronous programs.
ACM Trans. Embedded Comput. Syst., 2014

Constructive polychronous systems.
Sci. Comput. Program., 2014

Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions.
Design Autom. for Emb. Sys., 2014

2013
Embedding Polychrony into Synchrony.
IEEE Trans. Software Eng., 2013

Clock refinement in imperative synchronous languages.
EURASIP J. Emb. Sys., 2013

2012
Out-Of-order execution of synchronous data-flow networks.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Preservation of LTL properties in desynchronized systems.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Efficient Handling of Arrays in Dataflow Process Networks.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Monitoring distributed reactive systems.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

2011
SMT-based optimization for synchronous programs.
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011

Translating Synchronous Systems to Data-Flow Process Networks.
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011

Round Trip to Asynchrony and Synchrony.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Causality analysis of synchronous programs with refined clocks.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Schizophrenia and causality in the context of refined clocks.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Integrating system descriptions by clocked guarded actions.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Data-Flow Analysis of Extended Finite State Machines.
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

2010
Message from the chairs.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Compilation of imperative synchronous programs with refined clocks.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

From Synchronous Guarded Actions to SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Translating concurrent action oriented specifications to synchronous guarded actions.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Dependency-Driven Distribution of Synchronous Programs.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

Multithreaded code from synchronous programs: Extracting independent threads for OpenMP.
Proceedings of the Design, Automation and Test in Europe, 2010

A Formal Semantics of Clock Refinement in Imperative Synchronous Languages.
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

The Model Checking View to Clock Gating and Operand Isolation.
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

2009
Separate compilation for synchronous programs.
Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, 2009

Static data-flow analysis of synchronous programs.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Using IP Cores in Synchronous Languages.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Desynchronizing Synchronous Programs by Modes.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

2008
Formal Reasoning About Causality Analysis.
Proceedings of the Theorem Proving in Higher Order Logics, 21st International Conference, 2008

Hardware Acceleration for Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Performing causality analysis by bounded model checking.
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008

2007
A layered approach to polygon processing for safety-critical embedded systems.
PhD thesis, 2007

How Different are Esterel and SystemC?.
Proceedings of the Forum on specification and Design Languages, 2007

2006
A Verified Compiler for Synchronous Programs with Local Declarations.
Electr. Notes Theor. Comput. Sci., 2006

Efficient Map Overlay for Safety-Critical Embedded Systems.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Efficient code generation from synchronous programs.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Modular Compilation of Synchronous Programs.
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006

System Description Aspects as Syntactic Sugar.
Proceedings of the Forum on specification and Design Languages, 2006

2005
Using Three-Valued Logic to Specify and Verify Algorithms of Computational Geometry.
Proceedings of the Formal Methods and Software Engineering, 2005

Dependable Polygon-Processing Algorithms for Safety-Critical Embedded Systems.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Maximal Causality Analysis.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
Causality analysis of synchronous programs with delayed actions.
Proceedings of the 2004 International Conference on Compilers, 2004


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