Issues in the test of artificial neural networks. - Frank Warkowski; Jens Leenstra; Jos Nijhuis; Lambert Spaanenburg (ICCD, 1989)

On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. - Jens Leenstra; Lambert Spaanenburg (ITC, 1989)

On structured gate forest VLSI design. - Gerhard Roos; Jens Leenstra; Thomas Schwederski; Lambert Spaanenburg; Bernd Höfflinger (Microprocessing and Microprogramming, 1989)

Hierarchical test assembly for macro based VLSI design. - Jens Leenstra; Lambert Spaanenburg (ITC, 1990)

Hierarchical Test Program Development for Scan Testable Circuits. - Jens Leenstra; Lambert Spaanenburg (ITC, 1991)

Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. - Jörg A. Walter; Jens Leenstra; Gerhard Döttling; Bernd Leppla; Hans-Jürgen Münster; Kevin W. Kark; Bruce Wile (DAC, 1997)

Custom circuit design as a driver of microprocessor performance. - David H. Allen; Sang H. Dhong; H. Peter Hofstee; Jens Leenstra; Kevin J. Nowka; Daniel L. Stasiak; Dieter F. Wendel (IBM J. Res. Dev., 2000)

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. - Michael Kessler; Gundolf Kiefer; Jens Leenstra; Knut Schünemann; Thomas Schwarz; Hans-Joachim Wunderlich (ITC, 2001)

A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. - Jens Leenstra; Jürgen Pille; Antje Müller; Wolfram M. Sauer; Rolf Sautter; Dieter F. Wendel (IEEE J. Solid State Circuits, 2001)

The vector fixed point unit of the synergistic processor element of the cell architecture processor. - Nicolas Mäding; Jens Leenstra; Jürgen Pille; Rolf Sautter; Stefan Büttner; Sebastian Ehrenreich; W. Haller (ESSCIRC, 2005)

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. - Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Mäding; Jens Leenstra (ITC, 2006)

The microarchitecture of the synergistic processor for a cell processor. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IEEE J. Solid State Circuits, 2006)

Scan Test Planning for Power Reduction. - Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Mäding; Jens Leenstra (DAC, 2007)

IBM POWER6 accelerators: VMX and DFU. - Lee Eisen; John Wesley Ward III; Hans-Werner Tast; Nicolas Mäding; Jens Leenstra; Silvia M. Müller; Christian Jacobi 002; Jochen Preiss; Eric M. Schwarz; Steven R. Carlough (IBM J. Res. Dev., 2007)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)

Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. - Joachim Fenkes; Tobias Gemmeke; Jens Leenstra (J. Low Power Electron., 2007)

Scan chain clustering for test power reduction. - Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra; Nicolas Mäding (DAC, 2008)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

DB2 with BLU Acceleration: So Much More than Just a Column Store. - Vijayshankar Raman; Gopi K. Attaluri; Ronald Barber; Naresh Chainani; David Kalmuk; Vincent KulandaiSamy; Jens Leenstra; Sam Lightstone; Shaorong Liu; Guy M. Lohman; Tim Malkemus; René Müller 001; et al. (Proc. VLDB Endow., 2013)

POWER8 design methodology innovations for improving productivity and reducing power. - Matthew M. Ziegler; Ruchir Puri; Bob Philhower; Robert L. Franch; Wing K. Luk; Jens Leenstra; Peter Verwegen; Niels Fricke; George Gristede; Eric Fluhr; Victor V. Zyuban (CICC, 2014)

IBM POWER8 processor core microarchitecture. - Balaram Sinharoy; James Van Norstrand; Richard J. Eickemeyer; Hung Q. Le; Jens Leenstra; Dung Q. Nguyen; B. Konigsburg; K. Ward; M. D. Brown; José E. Moreira; D. Levitan; S. Tung; et al. (IBM J. Res. Dev., 2015)

Advanced features in IBM POWER8 systems. - Balaram Sinharoy; Randal C. Swanberg; Naresh Nayar; Bruce G. Mealey; Jeffrey Stuecheli; Berni Schiefer; Jens Leenstra; Joefon Jann; P. Oehler; D. Levitan; S. Eisen; D. Sanner; et al. (IBM J. Res. Dev., 2015)