Design of a Fully Parallel Viterbi Decoder. - Jens Sparsø; Steen Pedersen; Erik Paaske (VLSI, 1991)

An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders. - Erik Paaske; Steen Pedersen; Jens Sparsø (Integr., 1991)

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures. - Jens Sparsø; Henrik N. Jorgensen; Erik Paaske; Steen Pedersen; Thomas Rubner-Petersen (IEEE J. Solid State Circuits, 1991)

Design of delay insensitive circuits using multi-ring structures. - Jens Sparsø; Jørgen Staunstrup; Michael Dantzer-Sørensen (EURO-DAC, 1992)

Design of Self-timed Multipliers: A Comparison. - Jens Sparsø; Christian D. Nielsen; Lars Skovby Nielsen; Jørgen Staunstrup (Asynchronous Design Methodologies, 1993)

Delay-insensitive multi-ring structures. - Jens Sparsø; Jørgen Staunstrup (Integr., 1993)

Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. - Lars Skovby Nielsen; Cees Niessen; Jens Sparsø; Kees van Berkel 001 (IEEE Trans. Very Large Scale Integr. Syst., 1994)

A low-power asynchronous data-path for a FIR filter bank. - Lars Skovby Nielsen; Jens Sparsø (ASYNC, 1996)

The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. - Kåre Tais Christensen; Peter Jensen; Peter Korger; Jens Sparsø (ASYNC, 1998)

Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid. - Lars Skovby Nielsen; Jens Sparsø (Proc. IEEE, 1999)

Future directions in clocking multi-ghz systems. - Vojin G. Oklobdzija; Jens Sparsø (ISLPED, 2002)

Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. - Sune Fallgaard Nielsen; Jens Sparsø; Jan Madsen (DSD, 2004)

A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. - Tobias Bjerregaard; Shankar Mahadevan; Jens Sparsø (PATMOS, 2004)

A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. - Özgün Paker; Jens Sparsø; Niels Haandbæk; Mogens Isager; Lars Skovby Nielsen (J. VLSI Signal Process., 2004)

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. - Tobias Bjerregaard; Jens Sparsø (ASYNC, 2005)

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. - Tobias Bjerregaard; Jens Sparsø (DATE, 2005)

A Network Traffic Generator Model for Fast Network-on-Chip Simulation. - Shankar Mahadevan; Federico Angiolini; Michael Storgaard; Rasmus Grøndahl Olsen; Jens Sparsø; Jan Madsen (DATE, 2005)

An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. - Tobias Bjerregaard; Shankar Mahadevan; Rasmus Grøndahl Olsen; Jens Sparsø (SoC, 2005)

A Traffic Injection Methodology with Support for System-Level Synchronization. - Shankar Mahadevan; Federico Angiolini; Jens Sparsø; Luca Benini; Jan Madsen (VLSI-SoC, 2005)

Packetizing OCP Transactions in the MANGO Network-on-Chip. - Tobias Bjerregaard; Jens Sparsø (DSD, 2006)

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. - Mikkel Bystrup Stensgaard; Tobias Bjerregaard; Jens Sparsø; Johnny Halkjær Pedersen (DSD, 2006)

A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. - Tobias Bjerregaard; Mikkel Bystrup Stensgaard; Jens Sparsø (DATE, 2007)

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. - Mikkel Bystrup Stensgaard; Jens Sparsø (NOCS, 2008)

A Reactive and Cycle-True IP Emulator for MPSoC Exploration. - Shankar Mahadevan; Federico Angiolini; Jens Sparsø; Luca Benini; Jan Madsen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow. - Sune Fallgaard Nielsen; Jens Sparsø; Jonas Braband Jensen; Johan Sebastian Rosenkilde Nielsen (ASYNC, 2009)

Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. - Matthias Bo Stuart; Mikkel Bystrup Stensgaard; Jens Sparsø (CODES+ISSS, 2009)

Current trends in high-level synthesis of asynchronous circuits. - Jens Sparsø (ICECS, 2009)

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend. - Sune Fallgaard Nielsen; Jens Sparsø; Jan Madsen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study. - Omer Can Akgun; Joachim Neves Rodrigues; Jens Sparsø (ASYNC, 2010)

Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection. - Omer Can Akgun; Joachim Neves Rodrigues; Jens Sparsø (IET Comput. Digit. Tech., 2011)

Analytical derivation of traffic patterns in cache-coherent shared-memory systems. - Matthias Bo Stuart; Jens Sparsø (Microprocess. Microsystems, 2011)

The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation. - Matthias Bo Stuart; Mikkel Bystrup Stensgaard; Jens Sparsø (ACM Trans. Embed. Comput. Syst., 2011)

Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip. - Jens Sparsø (ACSD, 2012)

A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems. - Martin Schoeberl; Florian Brandner; Jens Sparsø; Evangelia Kasapaki (NOCS, 2012)

A light-weight statically scheduled network-on-chip. - Rasmus Bo Sørensen; Martin Schoeberl; Jens Sparsø (NORCHIP, 2012)

An area-efficient network interface for a TDM-based network-on-chip. - Jens Sparsø; Evangelia Kasapaki; Martin Schoeberl (DATE, 2013)

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip. - Evangelia Kasapaki; Jens Sparsø; Rasmus Bo Sørensen; Kees Goossens (DSD, 2013)

A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. - Christoph Thomas Muller; Steffen Malkowsky; Oskar Andersson; Babak Mohammadi; Jens Sparsø; Joachim Neves Rodrigues (VLSI-SoC, 2013)

Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers. - Evangelia Kasapaki; Jens Sparsø (ASYNC, 2014)

A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip. - Rasmus Bo Sørensen; Jens Sparsø; Mark Ruvald Pedersen; Jaspur Hojgaard (ISORC, 2014)

A loosely synchronizing asynchronous router for TDM-scheduled NOCs. - I. Kotleas; D. Humphreys; Rasmus Bo Sørensen; Evangelia Kasapaki; Florian Brandner; Jens Sparsø (NOCS, 2014)

Open core protocol (OCP) clock domain crossing interfaces. - Mathias Herlev; Christian Keis Poulsen; Jens Sparsø (NORCHIP, 2014)

Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools. - Christoph Thomas Muller; Evangelia Kasapaki; Rasmus Bo Sørensen; Jens Sparsø (NORCHIP, 2014)

A Time-Predictable Memory Network-on-Chip. - Martin Schoeberl; David Vh Chong; Wolfgang Puffitsch; Jens Sparsø (WCET, 2014)

The Argo NOC: Combining TDM and GALS. - Evangelia Kasapaki; Jens Sparsø (ECCTD, 2015)

Models of Communication for Multicore Processors. - Martin Schoeberl; Rasmus Bo Sørensen; Jens Sparsø (ISORC Workshops, 2015)

Message Passing on a Time-predictable Multicore Processor. - Rasmus Bo Sørensen; Wolfgang Puffitsch; Martin Schoeberl; Jens Sparsø (ISORC, 2015)

Interfacing hardware accelerators to a time-division multiplexing network-on-chip. - Luca Pezzarossa; Rasmus Bo Sørensen; Martin Schoeberl; Jens Sparsø (NORCAS, 2015)

T-CREST: Time-predictable multi-core architecture for embedded systems. - Martin Schoeberl; Sahar Abbaspour; Benny Akesson; Neil C. Audsley; Raffaele Capasso; Jamie Garside; Kees Goossens; Sven Goossens; Scott Hansen; Reinhold Heckmann; Stefan Hepp; Benedikt Huber; et al. (J. Syst. Archit., 2015)

An area-efficient TDM NoC supporting reconfiguration for mode changes. - Rasmus Bo Sørensen; Luca Pezzarossa; Jens Sparsø (NOCS, 2016)

Avionics Applications on a Time-Predictable Chip-Multiprocessor. - André Rocha; Cláudio Silva 002; Rasmus Bo Sørensen; Jens Sparsø; Martin Schoeberl (PDP, 2016)

Reconfiguration in FPGA-based multi-core platforms for hard real-time applications. - Luca Pezzarossa; Martin Schoeberl; Jens Sparsø (ReCoSoC, 2016)

State-based Communication on Time-predictable Multicore Processors. - Rasmus Bo Sørensen; Martin Schoeberl; Jens Sparsø (RTNS, 2016)

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation. - Evangelia Kasapaki; Martin Schoeberl; Rasmus Bo Sørensen; Christoph Thomas Muller; Kees Goossens; Jens Sparsø (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. - Luca Pezzarossa; Martin Schoeberl; Jens Sparsø (ISORC, 2017)

Timing Organization of a Real-Time Multicore Processor. - Martin Schoeberl; Jens Sparsø (NGCAS, 2017)

High-level synthesis for reduction of WCET in real-time systems. - Andreas Toftegaard Kristensen; Luca Pezzarossa; Jens Sparsø (NORCAS, 2017)

Can real-time systems benefit from dynamic partial reconfiguration? - Luca Pezzarossa; Andreas Toftegaard Kristensen; Martin Schoeberl; Jens Sparsø (NORCAS, 2017)

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip. - Rasmus Bo Sørensen; Luca Pezzarossa; Martin Schoeberl; Jens Sparsø (J. Syst. Archit., 2017)

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol. - Eleftherios Kyriakakis; Jens Sparsø; Martin Schoeberl (RTNS, 2018)

A Multicore Processor for Time-Critical Applications. - Martin Schoeberl; Luca Pezzarossa; Jens Sparsø (IEEE Des. Test, 2018)

Using dynamic partial reconfiguration of FPGAs in real-Time systems. - Luca Pezzarossa; Andreas Toftegaard Kristensen; Martin Schoeberl; Jens Sparsø (Microprocess. Microsystems, 2018)

Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016. - Jens Sparsø (Microprocess. Microsystems, 2018)

A Minimal Network Interface for a Simple Network-on-Chip. - Martin Schoeberl; Luca Pezzarossa; Jens Sparsø (ARCS, 2019)

Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking. - Adrian Mardari; Zuzana Jelcicová; Jens Sparsø (ASYNC, 2019)

Scratchpad Memories with Ownership. - Martin Schoeberl; Tórur Biskopstø Strøm; Oktay Baris; Jens Sparsø (DATE, 2019)

Implementing time-triggered communication over a standard ethernet switch. - Eleftherios Kyriakakis; Jens Sparsø; Martin Schoeberl (IoT-Fog@IoTDI, 2019)

Demonstration of a Time-predictable Flight Controller on a Multicore Processor. - Oktay Baris; Shibarchi Majumder; Tórur Biskopstø Strøm; Anders la Cour-Harbo; Jens Sparsø; Thomas Bak; Martin Schoeberl (ISORC, 2019)

A Time-predictable TTEthenet Node. - Maja Lund; Luca Pezzarossa; Jens Sparsø; Martin Schoeberl (ISORC, 2019)

S4NOC: a minimalistic network-on-chip for real-time multicores. - Martin Schoeberl; Luca Pezzarossa; Jens Sparsø (NoCArc@MICRO, 2019)

Hardlock: Real-time multicore locking. - Tórur Biskopstø Strøm; Jens Sparsø; Martin Schoeberl (J. Syst. Archit., 2019)

A Neural Network Engine for Resource Constrained Embedded Systems. - Zuzana Jelcicová; Adrian Mardari; Oskar Andersson; Evangelia Kasapaki; Jens Sparsø (ACSSC, 2020)

Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress. - Eleftherios Kyriakakis; Jens Sparsø; Peter P. Puschner; Martin Schoeberl (EMSOFT, 2020)

A time-predictable open-source TTEthernet end-system. - Eleftherios Kyriakakis; Maja Lund; Luca Pezzarossa; Jens Sparsø; Martin Schoeberl (J. Syst. Archit., 2020)

Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller. - Eleftherios Kyriakakis; Jens Sparsø; Martin Schoeberl (ETFA, 2021)

PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks. - Zuzana Jelcicová; Rasmus Jones; David Thorn Blix; Marian Verhelst; Jens Sparsø (EUSIPCO, 2021)

Synchronizing Real-Time Tasks in Time-Triggered Networks. - Eleftherios Kyriakakis; Jens Sparsø; Peter P. Puschner; Martin Schoeberl (ISORC, 2021)

Comparing timed-division multiplexing and best-effort networks-on-chip. - Jens Sparsø; Hans Jakob Damsgaard; Dimitrios Katsamanis; Martin Schoeberl (J. Syst. Archit., 2022)

Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements. - Kasper Hesse; Tjark Petersen; Jens Sparsø (DSD, 2023)

A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks. - Zuzana Jelcicová; Evangelia Kasapaki; Oskar Andersson; Jens Sparsø (ISCAS, 2023)

Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting. - Riccardo Miccini; Alaa Zniber; Clément Laroche; Tobias Piechowiak; Martin Schoeberl; Luca Pezzarossa; Ouassim Karrakchou; Jens Sparsø; Mounir Ghogho (MLSP, 2023)

NeuralCasting: A Front-End Compilation Infrastructure for Neural Networks. - Alessandro Cerioli; Riccardo Miccini; Clément Laroche; Tobias Piechowiak; Luca Pezzarossa; Jens Sparsø; Martin Schoeberl (IOTSMS, 2024)

Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms. - Riccardo Miccini; Alessandro Cerioli; Clément Laroche; Tobias Piechowiak; Jens Sparsø; Luca Pezzarossa (CoRR, 2024)

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. - Zuzana Jelcicová; Evangelia Kasapaki; Oskar Andersson; Jens Sparsø (IEEE Trans. Very Large Scale Integr. Syst., 2024)