An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion. - Youn-Sik Park; Sung-Wook Lee; Bai-Sun Kong; Kwang-Il Park; Jeong-Don Ihm; Joo-Sun Choi; Young-Hyun Jun (ISCAS, 2008)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. - Jae-Woo Im; Woopyo Jeong; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (ISSCC, 2015)

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (ISSCC, 2016)

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. - Seungjae Lee 001; Jin-Yub Lee; Il-Han Park; Jong-Yeol Park; Sung-Won Yun; Minsu Kim 004; Jong-Hoon Lee; Min-Seok Kim; Kangbin Lee; Taeeun Kim; Byungkyu Cho; Dooho Cho; et al. (ISSCC, 2016)

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. - Woopyo Jeong; Jae-Woo Im; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (IEEE J. Solid State Circuits, 2016)

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. - Chulbum Kim; Ji-Ho Cho; Woopyo Jeong; Il-Han Park; Hyun Wook Park; Doo-Hyun Kim; Daewoon Kang; Sunghoon Lee; Ji-Sang Lee; Wontae Kim 004; Jiyoon Park; Yang-Lo Ahn; et al. (ISSCC, 2017)

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (IEEE J. Solid State Circuits, 2017)

A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. - Chulbum Kim; Doo-Hyun Kim; Woopyo Jeong; Hyun-Jin Kim; Il-Han Park; Hyun Wook Park; Jong-Hoon Lee; Jiyoon Park; Yang-Lo Ahn; Ji Young Lee; Seungbum Kim; Hyun-Jun Yoon; et al. (IEEE J. Solid State Circuits, 2018)

A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface. - Dongku Kang; Minsu Kim 004; Suchang Jeon; Wontaeck Jung; Jooyong Park; Gyo Soo Choo; Dong-Kyo Shim; Anil Kavala; Seungbum Kim; Kyung-Min Kang; Jiyoung Lee; Kuihan Ko; et al. (ISSCC, 2019)

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. - Yong-Hun Kim; Hyung-Jin Kim; Jaemin Choi; Min-Su Ahn; Dongkeon Lee; Seung-Hyun Cho; Dong-Yeon Park; Young-Jae Park; Min-Soo Jang; Yong-Jun Kim; Jinyong Choi; Sung-Woo Yoon; et al. (ISSCC, 2021)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. - Jinook Jung; Jun-Han Choi; Kyoung-Jun Roh; Jaewoo Park; Won-Mook Lim; Tae-Sung Kim; Han-Ki Jeong; Myoungbo Kwak; Jaeyoun Youn; Jeong-Don Ihm; Changsik Yoo; Youngdon Choi; et al. (A-SSCC, 2023)

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. - Kyeongtae Nam; Jaehyuk Kim; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Incheol Nam; Young-Hun Seo; et al. (VLSI Technology and Circuits, 2024)

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. - Jinook Jung; Jun-Han Choi; Kyoung-Jun Roh; Jaewoo Park; Won-Mook Lim; Tae-Sung Kim; Han-Ki Jeong; Myoungbo Kwak; Jaeyoun Youn; Jeong-Don Ihm; Changsik Yoo; Youngdon Choi; et al. (IEEE J. Solid State Circuits, 2024)

An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier. - Kyeongtae Nam; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Jaehyuk Kim; Incheol Nam; Young-Hun Seo; et al. (IEEE J. Solid State Circuits, 2025)