Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier. - Sangheon Lee; Jeonghwan Song; Changhyuk Seong; Jiyong Woo; Jong-Moon Choi; Soon-Chan Kwon; Ho-Joon Kim; Hyun-Suk Kang; Soo Gil Kim; Hoe Gwon Jung; Kee-Won Kwon; Hyunsang Hwang (VLSI Circuits, 2016)

30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell. - Kosuke Hatsuda; Katsuhiko Hoya; Ryosuke Takizawa; Fumiyoshi Matsuoka; Takaya Yasuda; Akira Katayama; Tadashi Miyakawa; Kazuyo Senju; Kazuki Okawa; Yuka Furukawa; Yu Shimada; Katsuya Kotake; et al. (ISSCC, 2025)