Efficient fully-floating double-sampling integrator for DeltaSigma ADCs. - Kyehyung Lee; Jeongseok Chae; Gabor C. Temes (ISCAS, 2008)

A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (ISSCC, 2008)

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (IEEE J. Solid State Circuits, 2008)

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. - Jeongseok Chae; Sanghyeon Lee; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2010)

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. - Sanghyeon Lee; Jeongseok Chae; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2011)

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits. - Chia-Hung Chen; Joseph Crop; Jeongseok Chae; Patrick Chiang 001; Gabor C. Temes (ISCAS, 2012)