Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm. - Sangbu Yun; Dongyun Kam; Jeongwon Choe; Byeong Yong Kong; Youngjoo Lee (ISCAS, 2020)

Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories. - Seungsik Moon; Jeongwon Choe; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology. - Jeongwon Choe; Youngjoo Lee (A-SSCC, 2021)

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks. - Changhyeon Kim; Dongyoung Rim; Jeongwon Choe; Dongyun Kam; Giyoon Park; Seokki Kim; Youngjoo Lee (A-SSCC, 2021)

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm. - Jeongwon Choe; Youngjoo Lee (IEEE J. Solid State Circuits, 2022)

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm. - Seungwoo Hong; Dongyun Kam; Sangbu Yun; Jeongwon Choe; Namyoon Lee; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 2.35 Gb/s/mm2 (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology. - Jeongwon Choe; Youngjoo Lee (VLSI Technology and Circuits, 2023)

On the Decoding Complexity of Error Correction Code Transformer. - Seungjun Kim; Jeongwon Choe; Youngjoo Lee (ICTC, 2024)

Cost-Efficient Partially-Parallel LDPC Decoder Architecture for 50G-PON Standard. - Jeongwon Choe; Youngjoo Lee (ISOCC, 2024)

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. - Dongyun Kam; Sangbu Yun; Jeongwon Choe; Zhengya Zhang; Namyoon Lee; Youngjoo Lee (ISSCC, 2024)

Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications. - Dain Park; Dongyun Kam; Sangbu Yun; Jeongwon Choe; Youngjoo Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

SLEEP-SAFE: Self-Supervised Learning for Estimating Electroencephalogram Patterns With Structural Analysis of Fatigue Evidence. - Wonjun Ko; Jeongwon Choe; Jonggu Kang (IEEE Access, 2025)

High-Throughput Software-Defined LDPC Encoder and Decoder With x86-Based Data-Level Parallelism. - Sangbu Yun; Jeongwon Choe; Youngjoo Lee (IEEE Trans. Veh. Technol., 2025)

Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min-Max Algorithm. - Jeongwon Choe; Youngjoo Lee (IEEE J. Solid State Circuits, 2025)