A new 3-layer rectilinear area router with obstacle avoidance. - Jer-Min Jou; Jau-Yien Lee (Integr., 1989)

An Efficient VLSI Switch-Box Router. - Jer-Min Jou; Jau-Yien Lee; Yachyang Sun; Jhing-Fa Wang (IEEE Des. Test Comput., 1990)

Library-Adaptively Integrated Data Path Synthesis for DSP Systems. - Jer-Min Jou; Shiann-Rong Kuang (ICCD, 1993)

A fast and memory-efficient diagnostic fault simulation for sequential circuits. - Jer-Min Jou; Shung-Chih Chen (ICCAD, 1994)

A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. - Jer-Min Jou; Shung-Chih Chen; Ren-Der Chen (ISCAS, 1994)

Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. - Jer-Min Jou; Ren-Der Chen; Shiann-Rong Kuang (ISCAS, 1994)

Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. - Jer-Min Jou; Shung-Chih Chen (ISCAS, 1995)

Serial diagnostic fault simulation for synchronous sequential circuits. - Shung-Chih Chen; Jer-Min Jou (Integr., 1997)

Diagnostic fault simulation for synchronous sequential circuits. - Shung-Chih Chen; Jer-Min Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. - Ren-Der Chen; Jer-Min Jou; Yeu-Horng Shiau (ASP-DAC, 1999)

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. - Jer-Min Jou; Pei-Yin Chen; Yeu-Horng Shiau; Ming-Shiang Liang (ASP-DAC, 1999)

A New Pipelined Architecture for Fuzzy Color Correction. - Jer-Min Jou; Shiann-Rong Kuang; Yeu-Horng Shiau (ASP-DAC, 1999)

An efficient method for the decomposition and resynthesis of speed-independent circuits. - Ren-Der Chen; Jer-Min Jou; Yeu-Horng Shiau (ICECS, 1999)

A grey prediction motion estimator for digital image processing. - Jer-Min Jou; Pei-Yin Chen; Yeu-Horng Shiau; Jian-Ming Sun (ICECS, 1999)

A fast and efficient lossless data-compression method. - Jer-Min Jou; Pei-Yin Chen (IEEE Trans. Commun., 1999)

The gray prediction search algorithm for block motion estimation. - Jer-Min Jou; Pei-Yin Chen; Jian-Ming Sun (IEEE Trans. Circuits Syst. Video Technol., 1999)

Adaptive arithmetic coding using fuzzy reasoning and grey prediction. - Pei-Yin Chen; Jer-Min Jou (Fuzzy Sets Syst., 2000)

An adaptive fuzzy logic controller: its VLSI architecture and applications. - Jer-Min Jou; Pei-Yin Chen; Sheng-Fu Yang (IEEE Trans. Very Large Scale Integr. Syst., 2000)

An efficient VLSI architecture for HMM-based speech recognition. - Jer-Min Jou; Yeu-Horng Shiau; Chen-Jen Huang (ICECS, 2001)

Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. - Jer-Min Jou; Yeu-Horng Shiau; Chin-Chi Liu (ISCAS (2), 2001)

An efficient blocking-matching algorithm based on fuzzy reasoning. - Pei-Yin Chen; Jer-Min Jou (IEEE Trans. Syst. Man Cybern. Part B, 2001)

Design of a dynamic pipelined architecture for fuzzy color correction. - Jer-Min Jou; Shiann-Rong Kuang; Yeu-Horng Shiau; Ren-Der Chen (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme. - Yeu-Horng Shiau; Jer-Min Jou; Chin-Chi Liu (IEICE Trans. Inf. Syst., 2004)

A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC). - Yuan-Long Jeang; Jer-Min Jou; Win-Hsien Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Novel Reconfigurable Computation Unit for DSP Applications. - Jer-Min Jou; Yun-Lung Lee; Chen-Yen Lin; Chien-Ming Sun (ISVLSI, 2007)

A high-speed and decentralized arbiter design for NoC. - Yun-Lung Lee; Jer-Min Jou; Yen-Yu Chen (AICCSA, 2009)

New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. - Jer-Min Jou; Sih-Sian Wu; Yun-Lung Lee; Cheng Chou; Yuan-Long Jeang (DAC, 2010)

Efficient design and generation of a multi-facet arbiter. - Jer-Min Jou; Yun-Lung Lee; Sih-Sian Wu (SASP, 2010)

An Optimal Round-Robin Arbiter Design for NoC. - Jer-Min Jou; Yun-Lung Lee (J. Inf. Sci. Eng., 2010)

Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis. - Jer-Min Jou; Yun-Lung Lee; Sih-Sian Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A Transaction-based Design Model and Its MPEG-2 Encoder Design. - Chun-Yu Chen; Yun-Lung Lee; Jer-Min Jou (ICS, 2014)

A Run-time Manager for Multithreading of Multi-core Systems. - Cheng-Hung Hsieh; Jer-Min Jou (ICS, 2014)