Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. - Jeremy Constantin; Andreas Burg 001; Frank K. Gürkaynak (ASAP, 2012)

Multi-core architecture design for ultra-low-power wearable health monitoring systems. - Ahmed Yasir Dogan; Jeremy Constantin; Martino Ruggiero; Andreas Burg 001; David Atienza (DATE, 2012)

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. - Jeremy Constantin; Ahmed Yasir Dogan; Oskar Andersson; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues; David Atienza; Andreas Burg 001 (VLSI-SoC, 2012)

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. - Jeremy Constantin; Ahmed Yasir Dogan; Oskar Andersson; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues; David Atienza; Andreas Burg 001 (VLSI-SoC (Selected Papers), 2012)

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. - Jeremy Constantin; Andreas Burg 001; Frank K. Gürkaynak (IACR Cryptol. ePrint Arch., 2012)

Low-power processor architecture exploration for online biomedical signal analysis. - Ahmed Yasir Dogan; Jeremy Constantin; David Atienza; Andreas Burg 001; Luca Benini (IET Circuits Devices Syst., 2012)

Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. - Ahmed Yasir Dogan; Rubén Braojos; Jeremy Constantin; Giovanni Ansaloni; Andreas Burg 001; David Atienza (DATE, 2013)

A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead. - Rubén Braojos; Ivan Beretta; Jeremy Constantin; Andreas Peter Burg; David Atienza (EUC, 2014)

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. - Jeremy Constantin; Lai Wang; Georgios Karakonstantis; Anupam Chattopadhyay; Andreas Burg 001 (DATE, 2015)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

Statistical fault injection for impact-evaluation of timing errors on application performance. - Jeremy Constantin; Andreas Peter Burg; Zheng Wang 020; Anupam Chattopadhyay; Georgios Karakonstantis (DAC, 2016)

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. - Jeremy Constantin; Andrea Bonetti; Adam Teman; Thomas Christoph Müller; Lorenz Schmid; Andreas Burg 001 (ESSCIRC, 2016)

A low-power correlator for wakeup receivers with algorithm pruning through early termination. - Reza Ghanaatian; Paul N. Whatmough; Jeremy Constantin; Adam Teman; Andreas Burg 001 (ISCAS, 2016)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems. - Jeremy Constantin; Raphaël Houlmann; Nicholas Preyss; Nino Walenta; Hugo Zbinden; Pascal Junod; Andreas Burg 001 (J. Signal Process. Syst., 2017)

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. - Andrea Bonetti; Jeremy Constantin; Adam Ternan; Andreas Burg 001 (ISCAS, 2018)

Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. - Linyan Mei; Mohit Dandekar; Dimitrios Rodopoulos; Jeremy Constantin; Peter Debacker; Rudy Lauwereins; Marian Verhelst (AICAS, 2019)