An ASIC-embedded content addressable memory with power-saving and design for test features. - Thomas Chadwick; Tarl Gordon; Rahul Nadkarni; Jeremy Rowland (CICC, 2001)

BIST controlled variable sense amp timing for 90nm embedded SRAM. - Ciaran J. Brennan; Steven Eustis; John Goss; A. Humphrey; Michael Ouellette; Jeremy Rowland; Michael Fragano (CICC, 2004)