A full current-mode sense amplifier for low-power SRAM applications. - Anh-Tuan Do; Jeremy Yung Shern Low; Zhi-Hui Kong; Kiat Seng Yeo; Joshua Yung Low Yung Lih (APCCAS, 2008)

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. - Anh-Tuan Do; Kiat Seng Yeo; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong (APCCAS, 2010)

A novel counter-based low complexity inner-product architecture for high speed inputs. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang; Jeremy Yung Shern Low (ISCAS, 2010)

A new RNS scaler for {2n - 1, 2n, 2n + 1}. - Jeremy Yung Shern Low; Chip-Hong Chang (ISCAS, 2011)

Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2n - 1, 2n, 2n + 1. - Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. - Anh-Tuan Do; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong; Xiaoliang Tan; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A unified {2n-1, 2n, 2n+1} RNS scaler with dual scaling constants. - Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (APCCAS, 2012)

A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. - Howard Tang; Joshua Yung Lih Low; Jeremy Yung Shern Low; Liter Siek; Ching-Chuen Jong; Chip-Hong Chang (APCCAS, 2012)

A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. - Joshua Yung Lih Low; Ching-Chuen Jong; Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2012)

A VLSI Efficient Programmable Power-of-Two Scaler for 2n-1, 2n, 2n+1 RNS. - Jeremy Yung Shern Low; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A signed integer programmable power-of-two scaler for {2n-1, 2n, 2n+1} RNS. - Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2013)

A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli. - Jeremy Yung Shern Low; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${ {2^{n}-1, 2^{n}, 2^{n}+1 }}$. - Thian Fatt Tay; Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Erratum to "Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}". - Thian Fatt Tay; Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2016)