Test Generation for an Iterative Design Flow with RTL Changes. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2022)

Fast Test Generation for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (VTS, 2022)

Generation of Two-Cycle Tests for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)