Initial and PBTI-induced traps and charges in Hf-based oxides/TiN stacks. - Gilles Reimbold; Jérôme Mitard; Xavier Garros; Charles Leroux; Gérard Ghibaudo; François Martin (Microelectron. Reliab., 2007)

Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (ISCAS, 2011)

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. - Tommaso Romeo; Luigi Pantisano; Eddy Simoen; Raymond Krom; Mitsuhiro Togo; N. Horiguchi; Jérôme Mitard; Aaron Thean; Guido Groeseneken; Cor Claeys; Felice Crupi (ESSDERC, 2012)

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. - Jacopo Franco; Ben Kaczer; Jérôme Mitard; Maria Toledano-Luque; Felice Crupi; Geert Eneman; Ph. J. Rousse; Tibor Grasser; M. Cho; Thomas Kauerauf; Liesbeth Witters; Geert Hellings; et al. (ICICDT, 2012)

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

Beyond-Si materials and devices for more Moore and more than Moore applications. - Nadine Collaert; AliReza Alian; Hiroaki Arimura; Geert Boccardi; Geert Eneman; Jacopo Franco; Tsvetan Ivanov; Dennis Lin; Jérôme Mitard; S. Ramesh; R. Rooyackers; Marc Schaekers; et al. (ICICDT, 2016)

Isolation of nanowires made on bulk wafers by ground plane doping. - Romain Ritzenthaler; Hans Mertens; An De Keersgieter; Jérôme Mitard; Dan Mocuta; N. Horiguchi (ESSDERC, 2017)

Scaling CMOS beyond Si FinFET: an analog/RF perspective. - Bertrand Parvais; Geert Hellings; Marko Simicic; Pieter Weckx; Jérôme Mitard; Doyoung Jang; V. Deshpande; B. van Liempc; Anabela Veloso; A. Vandooren; Niamh Waldron; Piet Wambacq; et al. (ESSDERC, 2018)

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. - Shimpei Yamaguchi; Liesbeth Witters; Jérôme Mitard; Geert Eneman; Geert Hellings; Andriy Hikavyy; Roger Loo; Naoto Horiguchi (Microelectron. Reliab., 2018)

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. - Shih-Hung Chen; Dimitri Linten; Geert Hellings; Marko Simicic; Ben Kaczer; Thomas Chiarella; Hans Mertens; Jérôme Mitard; Anda Mocuta; N. Horiguchi (IRPS, 2019)

Detecting Transistor Defects in Medical Systems Using a Multi Model Ensemble of Convolutional Neural Networks. - Hüsnü Murat Koçak; Ahmet Teoman Naskali; Özgün Pinarer; Jérôme Mitard (IEEE BigData, 2021)

Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications. - Hyungrock Oh; Attilio Belmonte; Manu Perumkunnil; Jérôme Mitard; Nouredine Rassoul; Gabriele Luca Donadio; Romain Delhougne; Arnaud Furnémont; Gouri Sankar Kar; Wim Dehaene (ESSDERC, 2021)

Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies. - Gerhard Rzepa; Markus Karner; Oskar Baumgartner; Georg Strof; Franz Schanovsky; Ferdinand Mitterbauer; Christian Kernstock; Hui-Wen Karner; Pieter Weckx; Geert Hellings; Dieter Claes; Zhicheng Wu; et al. (IRPS, 2021)

Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET. - Hiroaki Arimura; S. Brus; Jacopo Franco; Yusuke Oniki; A. Vandooren; T. Conard; B. T. Chan; B. Kannan; M. Samiee; W. Li; P. Deminskyi; E. Shero; et al. (VLSI Technology and Circuits, 2023)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Automatic Prediction of Metal-Oxide-Semiconductor Field-Effect Transistor Threshold Voltage Using Machine Learning Algorithm. - Seoyeon Choi; Dong Geun Park; Min Jung Kim; Seain Bang; Jungchun Kim; Seunghee Jin; Ki Seok Huh; Donghyun Kim; Jérôme Mitard; Cheol E. Han; Jae Woo Lee (Adv. Intell. Syst., 2023)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)