Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SOC, 2001)

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Jerome Quartana (DATE, 2002)

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. - Jerome Quartana; Salim Renane; Arnaud Baixas; Laurent Fesquet; Marc Renaudin (FPL, 2005)

Asynchronous Systems on Programmable Logic. - Laurent Fesquet; Jerome Quartana; Marc Renaudin (ReCoSoC, 2005)

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. - Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SoC, 2005)

Integrated Evaluation Platform for Secured Devices. - Pascal Manet; Jean-Baptiste Rigaud; Julien Francq; Marc Jeambrun; Assia Tria; Bruno Robisson; Jerome Quartana; Selma Laabidi (ReCoSoC, 2006)