Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms. - Lucas Bragança; Fredy A. M. Alves; Jeronimo Costa Penha; Gabriel T. P. Coimbra; Ricardo Ferreira 001; José Augusto Miranda Nacif (SAMOS, 2018)

From Java to FPGA: An Experience with the Intel HARP System. - Pedro Caldeira; Jeronimo Costa Penha; Lucas Bragança; Ricardo Ferreira 001; José Augusto Miranda Nacif; Renato Ferreira 001; Fernando Magno Quintão Pereira (SBAC-PAD, 2018)

A GPU/FPGA-Based K-Means Clustering Using a Parameterized Code Generator. - Jeronimo Costa Penha; Lucas Bragança; Kristtopher Coelho; Michael Canesche; Jansen Silva; Giovanni Comarela; José Augusto Miranda Nacif; Ricardo Ferreira 001 (WSCAD, 2018)

ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing. - Jeronimo Costa Penha; Lucas B. da Silva; Jansen Silva; Kristtopher Coelho; Hector P. Baranda; José Augusto Miranda Nacif; Ricardo Ferreira 001 (Concurr. Comput. Pract. Exp., 2019)

READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications. - Lucas Bragança da Silva; Ricardo S. Ferreira 001; Michael Canesche; Marcelo M. Menezes; Maria D. Vieira; Jeronimo Costa Penha; Peter Jamieson; José Augusto Miranda Nacif (ACM Trans. Embed. Comput. Syst., 2019)

An Open Source Custom K-means Generator for AWS Cloud FPGA Accelerators. - Lucas Bragança; Michael Canesche; Jeronimo Costa Penha; Westerley Carvalho; Giovanni Comarela; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (SBESC, 2021)

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime. - Lucas Bragança; Michael Canesche; Jeronimo Costa Penha; Josué Campos; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2023)

Gene regulatory accelerators on cloud FPGA. - Jeronimo Costa Penha; Lucas Bragança; Michael Canesche; Dener Ribeiro; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2023)