An EPR4 read/write channel with digital timing recovery. - G. Diwakar Vishakhadatta; Russell Croman; Marius Goldenberg; Jerrell P. Hein; Pradeep Katikaneni; Diana Kuai; Cathy Lee; Ion Constatin Tesu; Richard Trujillo; Ligang Zhang; Kent Anderson; Richard Behrens; et al. (IEEE J. Solid State Circuits, 1998)

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Ligang Zhang; Jerrell P. Hein (ISSCC, 2006)

A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. - Derrick C. Wei; Yunteng Huang; Bruno W. Garlepp; Jerrell P. Hein (ISSCC, 2006)

A 2.5-Gb/s Multi-Rate 0.25-$ mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Douglas Pastorello; Eric T. King; Qicheng Yu; Dan B. Kasha; Philip Steiner; Ligang Zhang; Jerrell P. Hein; Bruce Del Signore (IEEE J. Solid State Circuits, 2006)