Fair Mutual Exclusion with Unfair P and V Operations. - Alain J. Martin; Jerry R. Burch (Inf. Process. Lett., 1985)

Combining CTL, Trace Theory and Timing Models. - Jerry R. Burch (Automatic Verification Methods for Finite State Systems, 1989)

Modeling timing assumptions with trace theory. - Jerry R. Burch (ICCD, 1989)

Verifying Liveness Properties by Verifying Safety Properties. - Jerry R. Burch (CAV, 1990)

Sequential Circuit Verification Using Symbolic Model Checking. - Jerry R. Burch; Edmund M. Clarke; Kenneth L. McMillan; David L. Dill (DAC, 1990)

Using BDDs to Verify Multipliers. - Jerry R. Burch (DAC, 1991)

Representing Circuits More Efficiently in Symbolic Model Checking. - Jerry R. Burch; Edmund M. Clarke; David E. Long (DAC, 1991)

Symbolic Model Checking with Partitioned Transistion Relations. - Jerry R. Burch; Edmund M. Clarke; David E. Long (VLSI, 1991)

Efficient Boolean function matching. - Jerry R. Burch; David E. Long (ICCAD, 1992)

Delay Models for Verifying Speed-Dependent Asynchronous Circuits. - Jerry R. Burch (ICCD, 1992)

Symbolic Model Checking: 10^20 States and Beyond - Jerry R. Burch; Edmund M. Clarke; Kenneth L. McMillan; David L. Dill; L. J. Hwang (Inf. Comput., 1992)

Efficient verification of determinate speed-independent circuits. - Peter A. Beerel; Jerry R. Burch; Teresa H.-Y. Meng (ICCAD, 1993)

Modeling hierarchical combinational circuits. - Jerry R. Burch; David L. Dill; Elizabeth Wolf; Giovanni De Micheli (ICCAD, 1993)

Sufficient conditions for correct gate-level speed-independent circuits. - Peter A. Beerel; Jerry R. Burch; Teresa H.-Y. Meng (ASYNC, 1994)

Automatic verification of Pipelined Microprocessor Control. - Jerry R. Burch; David L. Dill (CAV, 1994)

Symbolic model checking for sequential circuit verification. - Jerry R. Burch; Edmund M. Clarke; David E. Long; Kenneth L. McMillan; David L. Dill (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Efficient validity checking for processor verification. - Robert B. Jones; David L. Dill; Jerry R. Burch (ICCAD, 1995)

Techniques for Verifying Superscalar Microprocessors. - Jerry R. Burch (DAC, 1996)

Mechanically Checking a Lemma Used in an Automatic Verification Tool. - Phillip J. Windley; Jerry R. Burch (FMCAD, 1996)

Safe BDD Minimization Using Don't Cares. - Youpyo Hong; Peter A. Beerel; Jerry R. Burch; Kenneth L. McMillan (DAC, 1997)

Robust latch mapping for combinational equivalence checking. - Jerry R. Burch; Vigyan Singhal (ICCAD, 1998)

Tight integration of combinational verification methods. - Jerry R. Burch; Vigyan Singhal (ICCAD, 1998)

Checking Combinational Equivalence of Speed-Independent Circuits. - Peter A. Beerel; Jerry R. Burch; Teresa H. Meng (Formal Methods Syst. Des., 1998)

Sibling-substitution-based BDD minimization using don't cares. - Youpyo Hong; Peter A. Beerel; Jerry R. Burch; Kenneth L. McMillan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. - Jerry R. Burch; Roberto Passerone; Alberto L. Sangiovanni-Vincentelli (ACSD, 2001)

Using Multiple Levels of Abstractions in Embedded Software Design. - Jerry R. Burch; Roberto Passerone; Alberto L. Sangiovanni-Vincentelli (EMSOFT, 2001)

Constraints specification at higher levels of abstraction. - Felice Balarin; Jerry R. Burch; Luciano Lavagno; Yosinori Watanabe; Roberto Passerone; Alberto L. Sangiovanni-Vincentelli (HLDVT, 2001)

Conservative approximations for heterogeneous design. - Roberto Passerone; Jerry R. Burch; Alberto L. Sangiovanni-Vincentelli (EMSOFT, 2004)

Detecting support-reducing bound sets using two-cofactor symmetries. - Jin S. Zhang; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Jerry R. Burch (ASP-DAC, 2005)

Using simulation and satisfiability to compute flexibilities in Boolean networks. - Alan Mishchenko; Jin S. Zhang; Subarnarekha Sinha; Jerry R. Burch; Robert K. Brayton; Malgorzata Chrzanowska-Jeske (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Linear cofactor relationships in Boolean functions. - Jin S. Zhang; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Jerry R. Burch (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Memory Modeling in ESL-RTL Equivalence Checking. - Alfred Kölbl; Jerry R. Burch; Carl Pixley (DAC, 2007)

Refinement preserving approximations for the design and verification of heterogeneous systems. - Roberto Passerone; Jerry R. Burch; Alberto L. Sangiovanni-Vincentelli (Formal Methods Syst. Des., 2007)