The detection of small size multiple faults by single fault test sets n programmable logic arrays. - Janusz Rajski; Jerzy Tyszer (Fehlertolerierende Rechensysteme, 1984)

Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1985)

The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1986)

Multiple fault diagnosis for interconnection networks for distributed systems. - Jerzy Tyszer (Microprocess. Microprogramming, 1988)

A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing. - Jerzy Tyszer (IEEE Trans. Computers, 1988)

Fault diagnosis of digital switching networks. - Andrzej Jajszczyk; Jerzy Tyszer (IEEE Trans. Commun., 1989)

On the Diagnostic Resolution of Signature Analysis. - Janusz Rajski; Jerzy Tyszer; Babak Salimi (ICCAD, 1990)

Interference faults testing for time switches. - Jerzy Tyszer (IEEE Trans. Commun., 1990)

On the diagnostic properties of linear feedback shift registers. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Test generation for pattern-sensitive faults in integrated switches. - Jerzy Tyszer (IEEE Trans. Commun., 1991)

Testing of three-stage switching networks for coupling faults. - Jerzy Tyszer (IEEE Trans. Commun., 1992)

Accumulator-Based Compaction of Test Responses. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1993)

Recursive Pseudoexhaustive Test Pattern Generation. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1993)

Test responses compaction in accumulators with rotate carry adders. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Test pattern generation based on arithmetic operations. - Sanjay Gupta; Janusz Rajski; Jerzy Tyszer (ICCAD, 1994)

Software Accelerated Functional Fault Simulation for Data-Path Architectures. - Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 1995)

On testable multipliers for fixed-width data path architectures. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ICCAD, 1995)

Hierarchical Functional-Fault Simulation for High-Level Synthesis. - Mark Kassab; Janusz Rajski; Jerzy Tyszer (ITC, 1995)

Arithmetic built-in self test for high-level synthesis. - Nilanjan Mukherjee 001; H. Kassab; Janusz Rajski; Jerzy Tyszer (VTS, 1995)

Decompression of test data using variable-length seed LFSRs. - Nadime Zacharia; Janusz Rajski; Jerzy Tyszer (VTS, 1995)

Multiplicative Window Generators of Pseudo-random Test Vectors. - Janusz Rajski; Jerzy Tyszer (ED&TC, 1996)

Two-Dimensional Test Data Decompressor for Multiple Scan Designs. - Nadime Zacharia; Janusz Rajski; Jerzy Tyszer; John A. Waicukauski (ITC, 1996)

Broadband Time-Division Circuit Switching. - Andrzej Jajszczyk; Jerzy Tyszer (IEEE J. Sel. Areas Commun., 1996)

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. - Sanjay Gupta; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1996)

On Linear Dependencies in Subspaces of LFSR-Generated Sequences. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1996)

Parameterizable Testing Scheme for FIR Filters. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ITC, 1997)

Fault Diagnosis in Scan-Based BIST. - Janusz Rajski; Jerzy Tyszer (ITC, 1997)

Design of Testable Multipliers for Fixed-Width Data Paths. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1997)

Arithmetic built-in self-test for DSP cores. - Katarzyna Radecka; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Modular logic built-in self-test for IP cores. - Janusz Rajski; Jerzy Tyszer (ITC, 1998)

Automated synthesis of large phase shifters for built-in self-test. - Janusz Rajski; Nagesh Tamarapalli; Jerzy Tyszer (ITC, 1998)

Design of Phase Shifters for BIST Applications. - Janusz Rajski; Jerzy Tyszer (VTS, 1998)

Test Data Decompression for Multiple Scan Designs with Boundary Scan. - Janusz Rajski; Jerzy Tyszer; Nadime Zacharia (IEEE Trans. Computers, 1998)

Synthesis of pattern generators based on cellular automata with phase shifters. - Grzegorz Mrugalski; Jerzy Tyszer; Janusz Rajski (ITC, 1999)

Built-In Self-Test for Systems on Silicon. - Janusz Rajski; Jerzy Tyszer; Sanjay Patel (VLSI Design, 1999)

Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. - Janusz Rajski; Grzegorz Mrugalski; Jerzy Tyszer (VTS, 1999)

Testing of telecommunications hardware [Guest Editorial]. - Janusz Rajski; Jerzy Tyszer (IEEE Commun. Mag., 1999)

Diagnosis of Scan Cells in BIST Environment. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1999)

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. - Grzegorz Mrugalski; Jerzy Tyszer; Janusz Rajski (VTS, 2000)

Cellular automata-based test pattern generators with phase shifters. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Automated synthesis of phase shifters for built-in self-testapplications. - Janusz Rajski; Nagesh Tamarapalli; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Testing Schemes for FIR Filter Structures. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 2001)

Embedded Deterministic Test for Low-Cost Manufacturing Test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001; Rob Thompson; Kun-Han Tsai; Andre Hertwig; Nagesh Tamarapalli; Grzegorz Mrugalski; Geir Eide; Jun Qian (ITC, 2002)

On Compacting Test Response Data Containing Unknown Values. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Jerzy Tyszer (ICCAD, 2003)

Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. - Janusz Rajski; Jerzy Tyszer (ICCD, 2003)

Convolutional Compaction of Test Responses. - Janusz Rajski; Jerzy Tyszer; Chen Wang 014; Sudhakar M. Reddy (ITC, 2003)

High Speed Ring Generators and Compactors of Test Data. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (VTS, 2003)

2D Test Sequence Generators. - Grzegorz Mrugalski; Jerzy Tyszer; Janusz Rajski (IEEE Des. Test Comput., 2003)

Embedded Deterministic Test for Low-Cost Manufacturing. - Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Nagesh Tamarapalli; Jerzy Tyszer; Jun Qian (IEEE Des. Test Comput., 2003)

Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. - Janusz Rajski; Jerzy Tyszer (J. Electron. Test., 2003)

Fault Diagnosis in Designs with Convolutional Compactors. - Grzegorz Mrugalski; Chen Wang 014; Artur Pogiel; Jerzy Tyszer; Janusz Rajski (ITC, 2004)

Embedded Test for Low Cost Manufacturing. - Janusz Rajski; Nilanjan Mukherjee 001; Jerzy Tyszer; Thomas Rinderknecht (VLSI Design, 2004)

Planar High Performance Ring Generators. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (VTS, 2004)

Ring generators - new devices for embedded test applications. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Embedded deterministic test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Convolutional compaction-driven diagnosis of scan failures. - Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (ETS, 2005)

Diagnosis with convolutional compactors in presence of unknown states. - Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2005)

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. - Huaxing Tang; Chen Wang 014; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Irith Pomeranz (VLSI Design, 2005)

Synthesis of X-Tolerant Convolutional Compactors. - Janusz Rajski; Jerzy Tyszer (VTS, 2005)

Finite memory test response compactors for embedded test applications. - Janusz Rajski; Jerzy Tyszer; Chen Wang 014; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Test response compactor with programmable selector. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (DAC, 2006)

Convolutional Compactors with Variable Polynomials. - Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ETS, 2006)

X-Press Compactor for 1000x Reduction of Test Data. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2006)

High Performance Dense Ring Generators. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 2006)

New Test Data Decompressor for Low Power Applications. - Grzegorz Mrugalski; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (DAC, 2007)

Low Power Embedded Deterministic Test. - Dariusz Czysz; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (VTS, 2007)

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. - Jerzy Tyszer; Janusz Rajski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Mark Kassab; Wu-Tung Cheng; Manish Sharma; Liyang Lai (IEEE Des. Test Comput., 2007)

Isolation of Failing Scan Cells through Convolutional Test Response Compaction. - Grzegorz Mrugalski; Janusz Rajski; Chen Wang 014; Artur Pogiel; Jerzy Tyszer (J. Electron. Test., 2007)

Fault Diagnosis With Convolutional Compactors. - Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Low Power Scan Shift and Capture in the EDT Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. - Dariusz Czysz; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Compression based on deterministic vector clustering of incompatible test cubes. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (ITC, 2009)

Fault diagnosis for embedded read-only memories. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2009)

High-Speed On-Chip Event Counters for Embedded Systems. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (VLSI Design, 2009)

Defect Aware to Power Conscious Tests - The New DFT Landscape. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (VLSI Design, 2009)

Highly X-Tolerant Selective Compaction of Test Responses. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (VTS, 2009)

Low-Power Scan Operation in Test Compression Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Low power compression of incompatible test cubes. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Przemyslaw Szczerbicki; Jerzy Tyszer (ITC, 2010)

Dynamic channel allocation for higher EDT compression in SoC designs. - Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ITC, 2010)

On Compaction Utilizing Inter and Intra-Correlation of Unknown States. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Low Power Decompressor and PRPG with Constant Value Broadcast. - Michal Filipek; Yoshiaki Fukui; Hiroyuki Iwata; Grzegorz Mrugalski; Janusz Rajski; Masahiro Takakura; Jerzy Tyszer (Asian Test Symposium, 2011)

Power Aware Embedded Test. - Xijiang Lin; Elham K. Moghaddam; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jerzy Tyszer (Asian Test Symposium, 2011)

Fault Diagnosis in Memory BIST Environment with Non-march Tests. - Grzegorz Mrugalski; Artur Pogiel; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Pawel Urbanek (Asian Test Symposium, 2011)

Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. - Brady Benware; Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (ETS, 2011)

Reduced ATE Interface for High Test Data Compression. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ETS, 2011)

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. - Jakub Janicki; Jerzy Tyszer; Avijit Dutta; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2011)

Ring Generator: An Ultimate Linear Feedback Shift Register. - Nilanjan Mukherjee 001; Janusz Rajski; Grzegorz Mrugalski; Artur Pogiel; Jerzy Tyszer (Computer, 2011)

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. - Brady Benware; Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (J. Electron. Test., 2011)

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Przemyslaw Szczerbicki; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

BIST-Based Fault Diagnosis for Read-Only Memories. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Bandwidth-aware test compression logic for SoC designs. - Jakub Janicki; Jerzy Tyszer; Grzegorz Mrugalski; Janusz Rajski (ETS, 2012)

Low power test application with selective compaction in VLSI designs. - Dariusz Czysz; Janusz Rajski; Jerzy Tyszer (ITC, 2012)

Low power programmable PRPG with enhanced fault coverage gradient. - Jedrzej Solecki; Jerzy Tyszer; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2012)

Test generator with preselected toggling for low power built-in self-test. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Benoit Nadeau-Dostie (VTS, 2012)

EDT Bandwidth Management in SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

New test compression scheme based on low power BIST. - Jerzy Tyszer; Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ETS, 2013)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

Fault diagnosis of TSV-based interconnects in 3-D stacked designs. - Janusz Rajski; Jerzy Tyszer (ITC, 2013)

On Deploying Scan Chains for Data Storage in Test Compression Environment. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Des. Test, 2013)

Test Time Reduction in EDT Bandwidth Management for SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Low Power Test Compression with Programmable Broadcast-Based Control. - Sylwester Milewski; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (ATS, 2014)

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. - Maciej Trawka; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ATS, 2014)

On Using Implied Values in EDT-based Test Compression. - Marcin Gebala; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 2014)

Quality assurance in memory built-in self-test tools. - Albert Au; Artur Pogiel; Janusz Rajski; Piotr Sydow; Jerzy Tyszer; Justyna Zawada (DDECS, 2014)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. - Grzegorz Mrugalski; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Chen Wang 014 (ATS, 2015)

Design for low test pattern counts. - Haluk Konuk; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Deepak Solanki; Jerzy Tyszer; Justyna Zawada (DAC, 2015)

Embedded deterministic test points for compact cell-aware tests. - Cesar Acero; Derek Feltham; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Marek Patyra; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2015)

A deterministic BIST scheme based on EDT-compressed test patterns. - Grzegorz Mrugalski; Janusz Rajski; Lukasz Rybak 001; Jedrzej Solecki; Jerzy Tyszer (ITC, 2015)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low-Power Programmable PRPG With Test Compression Capabilities. - Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

On Test Points Enhancing Hardware Security. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ATS, 2016)

Minimal area test points for deterministic patterns. - Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Sudhakar M. Reddy; Janusz Rajski; Jerzy Tyszer (ITC, 2016)

Test point insertion in hybrid test compression/LBIST architectures. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2016)

On New Test Points for Compact Cell-Aware Tests. - Cesar Acero; Derek Feltham; Marek Patyra; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Des. Test, 2016)

ROM fault diagnosis for O(n2) test algorithms. - Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ETS, 2017)

Full-scan LBIST with capture-per-cycle hybrid test points. - Sylwester Milewski; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (ITC, 2017)

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. - Grzegorz Mrugalski; Janusz Rajski; Lukasz Rybak 001; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Embedded Deterministic Test Points. - Cesar Acero; Derek Feltham; Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Marek Patyra; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Trimodal Scan-Based Test Paradigm. - Grzegorz Mrugalski; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hypercompression of Test Patterns. - Yu Huang 005; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (ITC, 2018)

Deterministic Stellar BIST for In-System Automotive Test. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (ITC, 2018)

On New Class of Test Points and Their Applications. - Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2018)

Staggered ATPG with capture-per-cycle observation test points. - Yingdi Liu; Janusz Rajski; Sudhakar M. Reddy; Jedrzej Solecki; Jerzy Tyszer (VTS, 2018)

Hardware Protection via Logic Locking Test Points. - Michael Chen; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Test Time and Area Optimized BrST Scheme for Automotive ICs. - Nilanjan Mukherjee 001; Jerzy Tyszer; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki (ITC, 2019)

On Cyclic Scan Integrity Tests for EDT-based Compression. - Wu-Tung Cheng; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (VTS, 2019)

Logic BIST With Capture-Per-Clock Hybrid Test Points. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Test Sequence-Optimized BIST for Automotive Applications. - Bartosz Kaczmarek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Lukasz Rybak 001; Jerzy Tyszer (ETS, 2020)

X-Tolerant Tunable Compactor for In-System Test. - Yingdi Liu; Sylwester Milewski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Bartosz Wldarczak (ITC, 2020)

Scan Integrity Tests for EDT Compression. - Wu-Tung Cheng; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (IEEE Des. Test, 2020)

Low Cost Hypercompression of Test Data. - Yu Huang 005; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Deterministic Stellar BIST for Automotive ICs. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Convolutional Compaction-Based MRAM Fault Diagnosis. - Bartosz Grzelak; Martin Keim; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ETS, 2021)

On Reduction of Deterministic Test Pattern Sets. - Stephan Eggersglüß; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer (ITC, 2021)

Autonomous Scan Patterns for Laser Voltage Imaging. - Wu-Tung Cheng; Sylwester Milewski; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (IEEE Trans. Emerg. Top. Comput., 2021)

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. - Yingdi Liu; Sylwester Milewski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Time and Area Optimized Testing of Automotive ICs. - Nilanjan Mukherjee 001; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2021)

X-Masking for In-System Deterministic Test. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (ETS, 2022)

DIST: Deterministic In-System Test with X-masking. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (ITC, 2022)

Hardware Root of Trust for SSN-basedDFT Ecosystems. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (ITC, 2022)

LBIST for Automotive ICs With Enhanced Test Generation. - Bartosz Kaczmarek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Lukasz Rybak 001; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Hybrid Ring Generators for In-System Test Applications. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (ETS, 2023)

A New Static Compaction of Deterministic Test Sets. - Stephan Eggersglüß; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Lightweight True Random Number Generator for Root of Trust Applications. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

X-Masking for Deterministic In-System Tests. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Test Data Encryption with a New Stream Cipher. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (ITC, 2024)

Deterministic In-Fleet Scan Test for a Cloud Computing Platform. - Dan Trock; Subramanian Mahadevan; Nilanjan Mukherjee 001; Lee Harrison; Janusz Rajski; Jerzy Tyszer (ITC, 2024)

H2B: Crypto Hash Functions Based on Hybrid Ring Generators. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

The Future of Design for Test and Silicon Lifecycle Management. - Janusz Rajski; Vivek Chickermane; Jean-François Côté; Stephan Eggersglüß; Nilanjan Mukherjee 001; Jerzy Tyszer (IEEE Des. Test, 2024)

Identification of Failing Flip-Flops with Triangular Test Response Compaction. - Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (ETS, 2025)

A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Hybrid Ring Generators for In-System Testing. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (J. Electron. Test., 2025)

On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)