Security Testing for Hardware Products: The Security Evaluations Practice. - Alain Merle; Jessy Clédière (IOLTS, 2005)

What do S-boxes Say in Differential Side Channel Attacks? - Cécile Canovas; Jessy Clédière (IACR Cryptol. ePrint Arch., 2005)

A Proposition for Correlation Power Analysis Enhancement. - Thanh-Ha Le; Jessy Clédière; Cécile Canovas; Bruno Robisson; Christine Servière; Jean-Louis Lacoume (CHES, 2006)

Efficient Solution for Misalignment of Signal in Side Channel Analysis. - Thanh-Ha Le; Jessy Clédière; Christine Servière; Jean-Louis Lacoume (ICASSP (2), 2007)

Novel Approaches for Improving the Power Consumption Models in Correlation Analysis. - Thanh-Ha Le; Quoc-Thinh Nguyen-Vuong; Cécile Canovas; Jessy Clédière (IACR Cryptol. ePrint Arch., 2007)

Noise Reduction in Side Channel Attack Using Fourth-Order Cumulant. - Thanh-Ha Le; Jessy Clédière; Christine Servière; Jean-Louis Lacoume (IEEE Trans. Inf. Forensics Secur., 2007)

An overview of side channel analysis attacks. - Thanh-Ha Le; Cécile Canovas; Jessy Clédière (AsiaCCS, 2008)

Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. - Denis Réal; Cécile Canovas; Jessy Clédière; M'hamed Drissi; Frédéric Valette (DATE, 2008)

Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. - Gaetan Canivet; Jessy Clédière; Jean Baptiste Ferron; Frédéric Valette; Marc Renaudin; Régis Leveugle (IOLTS, 2008)

Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. - Gaetan Canivet; Régis Leveugle; Jessy Clédière; Frédéric Valette; Marc Renaudin (VTS, 2009)

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. - Gaetan Canivet; Paolo Maistri; Régis Leveugle; Frédéric Valette; Jessy Clédière; Marc Renaudin (ASAP, 2010)

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. - Gaetan Canivet; P. Maistn; Régis Leveugle; Frédéric Valette; Jessy Clédière; Marc Renaudin (ETS, 2010)

Influence of the temperature on true random number generators. - Mathilde Soucarros; Cécile Canovas-Dumas; Jessy Clédière; Philippe Elbaz-Vincent; Denis Réal (HOST, 2011)

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. - Gaetan Canivet; Paolo Maistri; Régis Leveugle; Jessy Clédière; Florent Valette; Marc Renaudin (J. Cryptol., 2011)

Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism. - Loïc Zussa; Jean-Max Dutertre; Jessy Clédière; Assia Tria (IOLTS, 2013)

Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor. - Mathilde Soucarros; Jessy Clédière; Cécile Canovas-Dumas; Philippe Elbaz-Vincent (J. Electron. Test., 2013)

Efficiency of a glitch detector against electromagnetic fault injection. - Loïc Zussa; Amine Dehbaoui; Karim Tobich; Jean-Max Dutertre; Philippe Maurine; Ludovic Guillaume-Sage; Jessy Clédière; Assia Tria (DATE, 2014)

Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter. - Loïc Zussa; Jean-Max Dutertre; Jessy Clédière; Bruno Robisson (HOST, 2014)

From Code Review to Fault Injection Attacks: Filling the Gap Using Fault Model Inference. - Louis Dureuil; Marie-Laure Potet; Philippe de Choudens; Cécile Dumas; Jessy Clédière (CARDIS, 2015)

Evidence of an information leakage between logically independent blocks. - Loïc Zussa; Ingrid Exurville; Jean-Max Dutertre; Jean-Baptiste Rigaud; Bruno Robisson; Assia Tria; Jessy Clédière (CS2@HiPEAC, 2015)

Nanofocused X-Ray Beam to Reprogram Secure Circuits. - Stéphanie Anceau; Pierre Bleuet; Jessy Clédière; Laurent Maingault; Jean-Luc Rainard; Rémi Tucoulou (CHES, 2017)

Fault Injection Characterization on Modern CPUs. - Thomas Trouchkine; Guillaume Bouffard; Jessy Clédière (WISTP, 2019)

Laboratory X-rays Operando Single Bit Attacks on Flash Memory Cells. - Laurent Maingault; Stéphanie Anceau; Manuel Sulmont; Luc Salvo; Jessy Clédière; Pierre Lhuissier; Emrick Beliard; Jean-Luc Rainard (CARDIS, 2021)

EM Fault Model Characterization on SoCs: From Different Architectures to the Same Fault Model. - Thomas Trouchkine; Guillaume Bouffard; Jessy Clédière (FDTC, 2021)

X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits. - S. Bouat; Stéphanie Anceau; Laurent Maingault; Jessy Clédière; Luc Salvo; Rémi Tucoulou (DFT, 2023)

Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis. - Clément Fanjas; Driss Aboulkassimi; Simon Pontié; Jessy Clédière (DFT, 2023)

PoP DRAM: A new EMFI approach based on EM-induced glitches on SoC. - Clément Fanjas; Driss Aboulkassimi; Simon Pontié; Jessy Clédière (FDTC, 2024)