DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache. - Darryl Aldrin M. Dioquino; Katrina Joy S. Rosario; Homer F. Supe; Jestoni V. Zarsuela; Anastacia P. Ballesil; Joy Alinda Reyes (ICECS, 2008)

A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design. - Jestoni V. Zarsuela; Anastacia B. Alvarez; Joy Alinda Reyes (UKSim, 2010)