Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications. - Jesús Lázaro 001; Jagoba Arias; José Luis Martín 001; Carlos Cuadrado (FPL, 2003)

An Electronic Secure Voting System Based on Automatic Paper Ballot Reading. - Iñaki Goirizelaia; Koldo Espinosa; José Luis Martín 001; Jesús Lázaro 001; Jagoba Arias; Juan J. Igarza (CIARP, 2004)

A Self-Reconfiguration Framework for Multiprocessor CSoPCs. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; José Luis Martín 001; Aitzol Zuloaga (FPL, 2004)

High Throughput Serpent Encryption Implementation. - Jesús Lázaro 001; Armando Astarloa; Jagoba Arias; Unai Bidarte; Carlos Cuadrado (FPL, 2004)

Doppler Location Algorithm for Wireless Sensor Networks. - Jagoba Arias; Jesús Lázaro 001; Aitzol Zuloaga; Jaime Jimenez (International Conference on Wireless Networks, 2004)

Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. - Armando Astarloa; Jesús Lázaro 001; Jagoba Arias; Unai Bidarte; Aitzol Zuloaga (MSV/AMCS, 2004)

Basque: A Case Study in Generalizing LaTeX Language Support. - Jagoba Arias; Jesús Lázaro 001; Juan M. Aguirregabiria (TEX, XML, and Digital Typography, 2004)

Malguki: an RSSI based ad hoc location algorithm. - Jagoba Arias; Aitzol Zuloaga; Jesús Lázaro 001; Jon Andreu; Armando Astarloa (Microprocess. Microsystems, 2004)

Hardware implementation of optical flow constraint equation using FPGAs. - José L. Martín-Sánchez; Aitzol Zuloaga; Carlos Cuadrado; Jesús Lázaro 001; Unai Bidarte (Comput. Vis. Image Underst., 2005)

Multiprocessor SoPC-Core for FAT volume computation. - Armando Astarloa; Unai Bidarte; Jesús Lázaro 001; Aitzol Zuloaga; Jagoba Arias (Microprocess. Microsystems, 2005)

Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications. - Jesús Lázaro 001; Jagoba Arias; José Luis Martín 001; Carlos Cuadrado; Armando Astarloa (Microprocess. Microsystems, 2005)

Node Synchronization in Wireless Sensor Networks. - Jagoba Arias; Eduardo Santos; Itziar Marín; Jaime Jimenez; Jesús Lázaro 001; Aitzol Zuloaga (ICWMC, 2006)

SOM Segmentation of gray scale images for optical recognition. - Jesús Lázaro 001; Jagoba Arias; José Luis Martín 001; Aitzol Zuloaga; Carlos Cuadrado (Pattern Recognit. Lett., 2006)

GPS-less location algorithm for wireless sensor networks. - Jagoba Arias; Jesús Lázaro 001; Aitzol Zuloaga; Jaime Jimenez; Armando Astarloa (Comput. Commun., 2007)

Hardware architecture for a general regression neural network coprocessor. - Jesús Lázaro 001; Jagoba Arias; Armando Astarloa; Unai Bidarte; Aitzol Zuloaga (Neurocomputing, 2007)

Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. - Armando Astarloa; Aitzol Zuloaga; Unai Bidarte; José Luis Martín 001; Jesús Lázaro 001; Jaime Jimenez (J. Syst. Archit., 2007)

Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. - Armando Astarloa; Unai Bidarte; Jaime Jimenez; Jesús Lázaro 001; Iñigo Martínez de Alegría (ATC, 2008)

Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. - Armando Astarloa; Unai Bidarte; Jesús Lázaro 001; Jon Andreu; José Luis Martín 001 (ReConFig, 2008)

AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. - Jesús Lázaro 001; Armando Astarloa; Unai Bidarte; Jaime Jimenez; Aitzol Zuloaga (ARC, 2009)

DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Jaime Jimenez (ICDCS Workshops, 2009)

PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Jaime Jimenez (ReConFig, 2009)

An Autonomous Fault Tolerant System for CAN Communications. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; José Luis Martín 001 (IEA/AIE (3), 2010)

Neuro semantic thresholding using OCR software for high precision OCR applications. - Jesús Lázaro 001; José Luis Martín 001; Jagoba Arias; Armando Astarloa; Carlos Cuadrado (Image Vis. Comput., 2010)

An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS. - Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001; Jaime Jimenez; Aitzol Zuloaga (SoC, 2011)

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. - Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Jaime Jimenez (ReConFig, 2011)

NoCmodel: An extensible framework for Network-on-Chips modeling. - Oscar Daniel Diaz; Armando Astarloa; Aitzol Zuloaga; Jesús Lázaro 001; Jaime Jimenez (ReCoSoC, 2011)

I2CSec: A secure serial Chip-to-Chip communication protocol. - Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Unai Bidarte; Jaime Jimenez (J. Syst. Archit., 2011)

High availability automation networks: PRP and HSR ring implementations. - Jose Angel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Alain García (ISIE, 2012)

Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA. - Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001; Mikel Garay; Javier Del Ser (ReConFig, 2012)

SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA. - Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001 (ARC, 2013)

SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems. - Stefanie Castillo; Armando Astarloa; Jesús Lázaro 001; Sergio Salas; Isaac Ballesteros (FPL, 2013)

Memory requirements analysis for PRP and HSR hardware implementations on FPGAs. - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Naiara Moreira; Alain García (IECON, 2013)

PRP and HSR version 1 (IEC 62439-3 Ed.2), improvements and a prototype implementation. - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Alain García (IECON, 2013)

Duplicate and circulating frames discard methods for PRP and HSR (IEC62439-3). - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Naiara Moreira (IECON, 2013)

System-on-Chip implementation of Reliable Ethernet Networks nodes. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Mikel Idirin (IECON, 2013)

IEEE 1588 Transparent Clock architecture for FPGA-based network devices. - Naiara Moreira; Armando Astarloa; Jesús Lázaro 001; Alain García; Enekoitz Ormaetxea (ISIE, 2013)

Fast and accurate SEU-tolerance characterization method for Zynq SoCs. - Igor Villata; Unai Bidarte; Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001 (FPL, 2014)

Securing IEEE 1588 messages with message authentication codes based on the KECCAK cryptographic algorithm implemented in FPGAs. - Naiara Moreira; Armando Astarloa; Uli Kretzschmar; Jesús Lázaro 001; Elias Molina (ISIE, 2014)

Cost-effective redundancy for ethernet train communications using HSR. - Aitzol Zuloaga; Armando Astarloa; Jaime Jimenez; Jesús Lázaro 001; Jose Angel Araujo (ISIE, 2014)

FTL-CFree: A Fuzzy Real-Time Language for Runtime Verification. - Joaquin Perez; Jaime Jimenez; Asier Rabanal; Armando Astarloa; Jesús Lázaro 001 (IEEE Trans. Ind. Informatics, 2014)

PRP and HSR for High Availability Networks in Power Utility Automation: A Method for Redundant Frames Discarding. - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Jose Ignacio Garate (IEEE Trans. Smart Grid, 2015)

Intelligent gateway for Industry 4.0-compliant production. - Armando Astarloa; Unai Bidarte; Jaime Jimenez; Aitzol Zuloaga; Jesús Lázaro 001 (IECON, 2016)

Cyber-Physical Production System Gateway Based on a Programmable SoC Platform. - Marcelo Urbina; Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Igor Villalta; Mikel Rodriguez (IEEE Access, 2017)

A novel BRAM content accessing and processing method based on FPGA configuration bitstream. - Julen Gomez-Cornejo; Aitzol Zuloaga; Igor Villalta; Javier Del Ser; Uli Kretzschmar; Jesús Lázaro 001 (Microprocess. Microsystems, 2017)

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. - Igor Villalta; Unai Bidarte; Julen Gomez-Cornejo; Jesús Lázaro 001; Armando Astarloa (Microelectron. Reliab., 2017)

On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems. - Naiara Moreira; Jesús Lázaro 001; Unai Bidarte; Jaime Jimenez; Armando Astarloa (IEEE Trans. Smart Grid, 2017)

System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. - Mikel Rodriguez; Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Jaime Jimenez (DCIS, 2018)

SEU emulation in industrial SoCs combining microprocessor and FPGA. - Igor Villalta; Unai Bidarte; Julen Gomez-Cornejo; Jaime Jimenez; Jesús Lázaro 001 (Reliab. Eng. Syst. Saf., 2018)

Fast and efficient FPGA prototype system for embedded control algorithms in electric traction. - Carlos Cuadrado; Iñigo Kortabarria; Jesús Lázaro 001; Unai Bidarte; Jaime Jiménez (DCIS, 2019)

Smart Sensor: SoC Architecture for the Industrial Internet of Things. - Marcelo Urbina; Tatiana Acosta; Jesús Lázaro 001; Armando Astarloa; Unai Bidarte (IEEE Internet Things J., 2019)

Electronic control board for student Rocket. - Jesús Lázaro 001; Laura Burgos; Leire Muguira; Armando Astarloa; Jaime Jiménez (DCIS, 2020)

Analysing the interference of Xen hypervisor in the network speed. - Sara Alonso; Jesús Lázaro 001; Jaime Jiménez; Leire Muguira; Alejandro Largacha (DCIS, 2020)

Synchronizing NTP Referenced SCADA Systems Interconnected by High-availability Networks. - Armando Astarloa; Mikel Rodriguez; Francisco Durán 003; Jaime Jiménez; Jesús Lázaro 001 (DCIS, 2020)

Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking. - Leire Muguira; Jesús Lázaro 001; Sara Alonso; Armando Astarloa; Mikel Rodriguez (DCIS, 2020)

Evaluating the OpenAMP framework in real-time embedded SoC platforms. - Sara Alonso; Jesús Lázaro 001; Jaime Jimenez; Leire Muguira; Unai Bidarte (DCIS, 2021)

A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems. - Mikel Rodriguez; Jesús Lázaro 001; Unai Bidarte; Jaime Jiménez; Armando Astarloa (IEEE Access, 2021)

Fast and efficient address search in System-on-a-Programmable-Chip using binary trees. - Jesús Lázaro 001; Unai Bidarte; Leire Muguira; Carlos Cuadrado; Jaime Jiménez (Comput. Electr. Eng., 2021)

The influence of virtualization on real-time systems' interrupts in embedded SoC platforms. - Sara Alonso; Jesús Lázaro 001; Jaime Jiménez; Leire Muguira; Unai Bidarte (DCIS, 2022)

Analysis and Deployment of Applications Acceleration Environment for Xilinx Hardware-Accelerated Platforms. - Adrián Santiago; Leire Muguira; Jaime Jiménez; Le Sun; Jesús Lázaro 001 (DCIS, 2022)

Design and development of an IoT device provided with a voice interface to improve treatment adherence in polymedicated patients. - José Luis Unibaso; José Ángel Araujo; Jesús Lázaro 001; Jaime Jiménez; Leire Muguira (DCIS, 2022)

High-Performance Computing Architecture for Sample Value Processing in the Smart Grid. - Le Sun; Leire Muguira; Jaime Jiménez; Armando Astarloa; Jesús Lázaro 001 (IEEE Access, 2022)

Embedded firewall for on-chip bus transactions. - Jesús Lázaro 001; Unai Bidarte; Leire Muguira; Armando Astarloa; Jaime Jiménez (Comput. Electr. Eng., 2022)

Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments. - Sara Alonso; Jesús Lázaro 001; Jaime Jiménez; Leire Muguira; Unai Bidarte (DCIS, 2023)

Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications. - Armando Astarloa; Pedro Fernández; Jesús Lázaro 001; Mikel Idirin; Sergio Salas (DCIS, 2023)

High Performance Platform to Detect Faults in the Smart Grid by Artificial Intelligence Inference. - Le Sun; Leire Muguira; Jaime Jiménez; Jesús Lázaro 001; Wang Yong (IEEE Trans. Smart Grid, 2024)

AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems. - Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; José Ángel Araujo; Jaime Jiménez (IEEE Trans. Reliab., 2024)

CRYSTALS-Dilithium post-quantum cyber-secure SoC for wired communications in critical systems. - Armando Astarloa; Jesús Lázaro 001; Jose Ignacio Garate (Internet Things, 2025)