A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. - Jente B. Kuang; Hung C. Ngo; Kevin J. Nowka; Jethro C. Law; Rajiv V. Joshi (ICCD, 2005)

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)