SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers. - Jeyavijayan Rajendran; Hetal Borad; Shyam Mantravadi; Ramesh Karri (HOST, 2010)

Towards a comprehensive and systematic classification of hardware Trojans. - Jeyavijayan Rajendran; Efstratios Gavas; Jorge Jimenez; Vikram Padman; Ramesh Karri (ISCAS, 2010)

Memristor based programmable threshold logic array. - Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose (NANOARCH, 2010)

Trustworthy Hardware: Identifying and Classifying Hardware Trojans. - Ramesh Karri; Jeyavijayan Rajendran; Kurt Rosenfeld; Mohammad Tehranipoor (Computer, 2010)

Blue team red team approach to hardware trust assessment. - Jeyavijayan Rajendran; Vinayaka Jyothi; Ramesh Karri (ICCD, 2011)

Parallel memristors: Improving variation tolerance in memristive digital circuits. - Jeyavijayan Rajendran; Ramesh Karri; Garrett S. Rose (ISCAS, 2011)

An Approach to Tolerate Process Related Variations in Memristor-Based Applications. - Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose (VLSI Design, 2011)

Design and analysis of ring oscillator based Design-for-Trust technique. - Jeyavijayan Rajendran; Vinayaka Jyothi; Ozgur Sinanoglu; Ramesh Karri (VTS, 2011)

Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges. - Mohammad Tehranipoor; Hassan Salmani; Xuehui Zhang; Michel Wang; Ramesh Karri; Jeyavijayan Rajendran; Kurt Rosenfeld (Computer, 2011)

Security analysis of logic obfuscation. - Jeyavijayan Rajendran; Youngok K. Pino; Ozgur Sinanoglu; Ramesh Karri (DAC, 2012)

Logic encryption: A fault analysis perspective. - Jeyavijayan Rajendran; Youngok K. Pino; Ozgur Sinanoglu; Ramesh Karri (DATE, 2012)

Engineering crossbar based emerging memory technologies. - Sachhidh Kannan; Jeyavijayan Rajendran; Ramesh Karri; Ozgur Sinanoglu (ICCD, 2012)

Nano-PPUF: A Memristor-Based Security Primitive. - Jeyavijayan Rajendran; Garrett S. Rose; Ramesh Karri; Miodrag Potkonjak (ISVLSI, 2012)

Nanoelectronic Solutions for Hardware Security. - Jeyavijayan Rajendran; Ramesh Karri; James B. Wendt; Miodrag Potkonjak; Nathan R. McDonald; Garrett S. Rose; Bryant T. Wysocki (IACR Cryptol. ePrint Arch., 2012)

Design Considerations for Multilevel CMOS/Nano Memristive Memory. - Harika Manem; Jeyavijayan Rajendran; Garrett S. Rose (ACM J. Emerg. Technol. Comput. Syst., 2012)

Leveraging Memristive Systems in the Construction of Digital Logic Circuits. - Garrett S. Rose; Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Robinson E. Pino (Proc. IEEE, 2012)

An Energy-Efficient Memristive Threshold Logic Circuit. - Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose (IEEE Trans. Computers, 2012)

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. - Harika Manem; Jeyavijayan Rajendran; Garrett S. Rose (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Hardware security strategies exploiting nanoelectronic circuits. - Garrett S. Rose; Jeyavijayan Rajendran; Nathan R. McDonald; Ramesh Karri; Miodrag Potkonjak; Bryant T. Wysocki (ASP-DAC, 2013)

Security analysis of integrated circuit camouflaging. - Jeyavijayan Rajendran; Michael Sam; Ozgur Sinanoglu; Ramesh Karri (CCS, 2013)

Is split manufacturing secure? - Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri (DATE, 2013)

Reconciling the IC test and security dichotomy. - Ozgur Sinanoglu; Naghmeh Karimi; Jeyavijayan Rajendran; Ramesh Karri; Yier Jin; Ke Huang 001; Yiorgos Makris (ETS, 2013)

Hardware security: threat models and metrics. - Masoud Rostami; Farinaz Koushanfar; Jeyavijayan Rajendran; Ramesh Karri (ICCAD, 2013)

High-level synthesis for security and trust. - Jeyavijayan Rajendran; Huan Zhang; Ozgur Sinanoglu; Ramesh Karri (IOLTS, 2013)

VLSI testing based security metric for IC camouflaging. - Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri (ITC, 2013)

Sneak-path Testing of Memristor-based Memories. - Sachhidh Kannan; Jeyavijayan Rajendran; Ramesh Karri; Ozgur Sinanoglu (VLSI Design, 2013)

A study on the effectiveness of Trojan detection techniques using a red team blue team approach. - Xuehui Zhang; Kan Xiao; Mohammad Tehranipoor; Jeyavijayan Rajendran; Ramesh Karri (VTS, 2013)

Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. - Jeyavijayan Rajendran; Arun K. Kanuparthi; Mohamed Zahran 001; Sateesh Addepalli; Gaston Ormazabal; Ramesh Karri (IEEE Des. Test, 2013)

A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. - Adam Waksman; Jeyavijayan Rajendran; Matthew Suozzo; Simha Sethumadhavan (DAC, 2014)

Shielding and securing integrated circuits with sensors. - Davood Shahrjerdi; Jeyavijayan Rajendran; Siddharth Garg; Farinaz Koushanfar; Ramesh Karri (ICCAD, 2014)

Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. - David H. K. Hoe; Jeyavijayan Rajendran; Ramesh Karri (ISVLSI, 2014)

Hot topic session 9C: Test and fault tolerance for emerging memory technologies. - Suriya Natarajan; Amitava Majumdar 002; Jeyavijayan Rajendran (VTS, 2014)

Regaining Trust in VLSI Design: Design-for-Trust Techniques. - Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri (Proc. IEEE, 2014)

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling. - Chen Liu 013; Jeyavijayan Rajendran; Chengmo Yang; Ramesh Karri (IEEE Trans. Emerg. Top. Comput., 2014)

Detecting malicious modifications of data in third-party intellectual property cores. - Jeyavijayan Rajendran; Vivekananda Vedula; Ramesh Karri (DAC, 2015)

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. - Jeyavijayan Rajendran; Ramesh Karri; James B. Wendt; Miodrag Potkonjak; Nathan R. McDonald; Garrett S. Rose; Bryant T. Wysocki (Proc. IEEE, 2015)

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. - Jeyavijayan Rajendran; Ramesh Karri; Garrett S. Rose (IEEE Trans. Computers, 2015)

Fault Analysis-Based Logic Encryption. - Jeyavijayan Rajendran; Huan Zhang; Chi Zhang; Garrett S. Rose; Youngok K. Pino; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Computers, 2015)

Belling the CAD: Toward Security-Centric Electronic System Design. - Jeyavijayan Rajendran; Aman Ali; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

The cat and mouse in split manufacturing. - Yujie Wang; Pu Chen; Jiang Hu; Jeyavijayan Rajendran (DAC, 2016)

Activation of logic encrypted chips: Pre-test or post-test? - Muhammad Yasin; Samah Mohamed Saeed; Jeyavijayan Rajendran; Ozgur Sinanoglu (DATE, 2016)

Controlling your control flow graph. - Arun K. Kanuparthi; Jeyavijayan Rajendran; Ramesh Karri (HOST, 2016)

Sneak path enabled authentication for memristive crossbar memories. - Md. Badruddoja Majumder; Mesbah Uddin; Garrett S. Rose; Jeyavijayan Rajendran (AsianHOST, 2016)

SARLock: SAT attack resistant logic locking. - Muhammad Yasin; Bodhisatwa Mazumdar; Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu (HOST, 2016)

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect. - Chaofei Yang; Beiye Liu; Hai Li 001; Yiran Chen 001; Wujie Wen; Mark Barnell; Qing Wu 002; Jeyavijayan Rajendran (ICCAD, 2016)

CamoPerturb: secure IC camouflaging for minterm protection. - Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran (ICCAD, 2016)

Hardware-based attacks to compromise the cryptographic security of an election system. - Mohammad-Mahdi Bidmeshki; Gaurav Rajavendra Reddy; Liwei Zhou; Jeyavijayan Rajendran; Yiorgos Makris (ICCD, 2016)

Securing pressure measurements using SensorPUFs. - Jeyavijayan Rajendran; Jack Tang; Ramesh Karri (ISCAS, 2016)

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. - Jeyavijayan Rajendran; Arunshankar Muruga Dhandayuthapany; Vivekananda Vedula; Ramesh Karri (VLSID, 2016)

Supply-Chain Security of Digital Microfluidic Biochips. - Sk Subidh Ali; Mohamed Ibrahim 002; Jeyavijayan Rajendran; Ozgur Sinanoglu; Krishnendu Chakrabarty (Computer, 2016)

Security Analysis of Anti-SAT. - Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran (IACR Cryptol. ePrint Arch., 2016)

On Improving the Security of Logic Locking. - Muhammad Yasin; Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. - Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Routing perturbation for enhanced security in split manufacturing. - Yujie Wang; Pu Chen; Jiang Hu; Jeyavijayan (JV) Rajendran (ASP-DAC, 2017)

Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization. - Giovanni Di Crescenzo; Jeyavijayan Rajendran; Ramesh Karri; Nasir D. Memon (ASHES@CCS, 2017)

Provably-Secure Logic Locking: From Theory To Practice. - Muhammad Yasin; Abhrajit Sengupta; Mohammed Thari Nabeel; Mohammed Ashraf; Jeyavijayan Rajendran; Ozgur Sinanoglu (CCS, 2017)

What to Lock?: Functional and Parametric Locking. - Muhammad Yasin; Abhrajit Sengupta; Benjamin Carrión Schäfer; Yiorgos Makris; Ozgur Sinanoglu; Jeyavijayan Rajendran (ACM Great Lakes Symposium on VLSI, 2017)

On designing optimal camouflaged layouts. - Thomas Broadfoot; Carl Sechen; Jeyavijayan (JV) Rajendran (HOST, 2017)

TTLock: Tenacious and traceless logic locking. - Muhammad Yasin; Bodhisatwa Mazumdar; Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu (HOST, 2017)

Making split fabrication synergistically secure and manufacturable. - Lang Feng 001; Yujie Wang; Jiang Hu; Wai-Kei Mak; Jeyavijayan Rajendran (ICCAD, 2017)

Front-end-of-line attacks in split manufacturing. - Yujie Wang; Tri Cao; Jiang Hu; Jeyavijayan Rajendran (ICCAD, 2017)

An overview of hardware intellectual property protection. - Jeyavijayan (JV) Rajendran (ISCAS, 2017)

DFS covert channels on multi-core platforms. - Murugappan Alagappan; Jeyavijayan Rajendran; Milos Doroslovacki; Guru Venkataramani (VLSI-SoC, 2017)

Innovative practices session 3C hardware security. - Jeyavijayan (JV) Rajendran; Peilin Song; Suriya Natarajan (VTS, 2017)

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. - Muhammad Yasin; Ozgur Sinanoglu; Jeyavijayan Rajendran (IEEE Trans. Inf. Forensics Secur., 2017)

Towards provably-secure performance locking. - Monir Zaman; Abhrajit Sengupta; Danqing Liu; Ozgur Sinanoglu; Yiorgos Makris; Jeyavijayan (JV) Rajendran (DATE, 2018)

Special session: Recent developments in hardware security. - Ro Cammarota; Naghmeh Karimi; Siddharth Garg; Jeyavijayan Rajendran (VTS, 2018)

When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs. - Ghada Dessouky; David Gens; Patrick Haney; Garrett Persyn; Arun K. Kanuparthi; Hareesh Khattri; Jason M. Fung; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (CoRR, 2018)

The Cat and Mouse in Split Manufacturing. - Yujie Wang; Pu Chen; Jiang Hu; Guofeng Li; Jeyavijayan Rajendran (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Layout recognition attacks on split manufacturing. - Wenbin Xu; Lang Feng 001; Jeyavijayan Rajendran; Jiang Hu (ASP-DAC, 2019)

SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis. - Muhammad Yasin; Chongzhi Zhao; Jeyavijayan (JV) Rajendran (ICCAD, 2019)

Red Teaming a Multi-Colored Bluetooth Bulb. - Ryan Vrecenar; Michael Hall; Joshua Zshiesche; Mahesh Naidu; Jeyavijayan Rajendran; Stavros Kalafatis (ICCD, 2019)

Breaking Analog Locking Techniques via Satisfiability Modulo Theories. - Nithyashankari Gummidipoondi Jayasankaran; Adriana C. Sanabria-Borbon; Amr Abuellil; Edgar Sánchez-Sinencio; Jiang Hu; Jeyavijayan Rajendran (ITC, 2019)

HardFails: Insights into Software-Exploitable Hardware Bugs. - Ghada Dessouky; David Gens; Patrick Haney; Garrett Persyn; Arun K. Kanuparthi; Hareesh Khattri; Jason M. Fung; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (USENIX Security Symposium, 2019)

Special Session: Countering IP Security threats in Supply chain. - Hassan Salmani; Tamzidul Hoque; Swarup Bhunia; Muhammad Yasin; Jeyavijayan (JV) Rajendran; Naghmeh Karimi (VTS, 2019)

Trustworthy Hardware Design: Combinational Logic Locking Techniques - Muhammad Yasin; Jeyavijayan Rajendran; Ozgur Sinanoglu (Springer, 2020)

Multi-Objective Strategies for Stripped-Functionality Logic Locking. - Zhaokun Han; Muhammad Yasin; Jeyavijayan (JV) Rajendran (ISCAS, 2020)

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. - Adriana C. Sanabria-Borbon; Nithyashankari Gummidipoondi Jayasankaran; S. Y. Lee; Edgar Sánchez-Sinencio; Jiang Hu; Jeyavijayan (JV) Rajendran (ITC, 2020)

Security of Cloud FPGAs: A Survey. - Chenglu Jin; Vasudev Gohil; Ramesh Karri; Jeyavijayan Rajendran (CoRR, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

Keynote: A Disquisition on Logic Locking. - Abhishek Chakraborty 001; Nithyashankari Gummidipoondi Jayasankaran; Yuntao Liu 001; Jeyavijayan Rajendran; Ozgur Sinanoglu; Ankur Srivastava 001; Yang Xie 001; Muhammad Yasin; Michael Zuzak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. - Chaofei Yang; Beiye Liu; Hai Li 001; Yiran Chen 001; Mark Barnell; Qing Wu 002; Wujie Wen; Jeyavijayan Rajendran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Removal Attacks on Logic Locking and Camouflaging Techniques. - Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran (IEEE Trans. Emerg. Top. Comput., 2020)

Breaking Analog Locking Techniques. - Nithyashankari Gummidipoondi Jayasankaran; Adriana C. Sanabria-Borbon; Amr Abuellil; Edgar Sánchez-Sinencio; Jiang Hu; Jeyavijayan Rajendran (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned. - Ahmad-Reza Sadeghi; Jeyavijayan Rajendran; Rahul Kande (ACM Great Lakes Symposium on VLSI, 2021)

Does logic locking work with EDA tools? - Zhaokun Han; Muhammad Yasin; Jeyavijayan (JV) Rajendran (USENIX Security Symposium, 2021)

Guest Editors' Introduction: Competing to Secure SoCs. - Siddharth Garg; Daniel E. Holcomb; Jeyavijayan (JV) Rajendran; Ahmad-Reza Sadeghi (IEEE Des. Test, 2021)

Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. - Adriana C. Sanabria-Borbon; Nithyashankari Gummidipoondi Jayasankaran; Jiang Hu; Jeyavijayan Rajendran; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing. - Vasudev Gohil; Mark Tressler; Kevin Sipple; Satwik Patnaik; Jeyavijayan Rajendran (IEEE Trans. Inf. Forensics Secur., 2021)

ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. - Vasudev Gohil; Hao Guo; Satwik Patnaik; Jeyavijayan Rajendran (CCS, 2022)

Trusting the trust anchor: towards detecting cross-layer vulnerabilities with hardware fuzzing. - Chen Chen 125; Rahul Kande; Pouya Mahmoody; Ahmad-Reza Sadeghi; J. V. Rajendran 001 (DAC, 2022)

Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. - Swarup Bhunia; Amitabh Das; Saverio Fazzari; Vivian Kammler; David Kehlet; Jeyavijayan Rajendran; Ankur Srivastava 001 (ICCAD, 2022)

Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. - Satwik Patnaik; Vasudev Gohil; Hao Guo; Jeyavijayan (JV) Rajendran (ISOCC, 2022)

TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. - Rahul Kande; Addison Crump; Garrett Persyn; Patrick Jauernig; Ahmad-Reza Sadeghi; Aakash Tyagi; Jeyavijayan Rajendran (USENIX Security Symposium, 2022)

Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security. - Srini Devadas; Jeyavijayan Rajendran (IEEE Des. Test, 2022)

Vulnerability Assessment of Ciphers To Fault Attacks Using Reinforcement Learning. - Hao Guo; Sayandeep Saha; Satwik Patnaik; Vasudev Gohil; Debdeep Mukhopadhyay; Jeyavijayan (JV) Rajendran (IACR Cryptol. ePrint Arch., 2022)

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. - Nithyashankari Gummidipoondi Jayasankaran; Adriana C. Sanabria-Borbon; Edgar Sánchez-Sinencio; Jiang Hu; Jeyavijayan Rajendran (IEEE Trans. Emerg. Top. Comput., 2022)

ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning. - Hao Guo; Sayandeep Saha; Vasudev Gohil; Satwik Patnaik; Debdeep Mukhopadhyay; Jeyavijayan (JV) Rajendran (DAC, 2023)

PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. - Chen Chen 125; Vasudev Gohil; Rahul Kande; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (ICCAD, 2023)

HyPFuzz: Formal-Assisted Processor Fuzzing. - Chen Chen 125; Rahul Kande; Nathan Nguyen; Flemming Andersen; Aakash Tyagi; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (USENIX Security Symposium, 2023)

FuncTeller: How Well Does eFPGA Hide Functionality? - Zhaokun Han; Mohammed Shayan; Aneesh Dixit; Mustafa M. Shihab; Yiorgos Makris; Jeyavijayan Rajendran (USENIX Security Symposium, 2023)

LLM-assisted Generation of Hardware Assertions. - Rahul Kande; Hammond Pearce; Benjamin Tan 001; Brendan Dolan-Gavitt; Shailja Thakur; Ramesh Karri; Jeyavijayan Rajendran (CoRR, 2023)

Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. - Nithyashankari Gummidipoondi Jayasankaran; Hao Guo; Satwik Patnaik; Jeyavijayan Rajendran; Jiang Hu (CoRR, 2023)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. - Jonathan Hao-Cheng Ku; Junyao Zhang; Haoxuan Shan; Saichand Samudrala; Jiawen Wu; Qilin Zheng; Ziru Li; Jeyavijayan Rajendran; Yiran Chen 001 (DAC, 2024)

Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection. - Mohamadreza Rostami; Shaza Zeitouni; Rahul Kande; Chen Chen 125; Pouya Mahmoody; Jeyavijayan Rajendran; Ahmad-Reza Sadeghi (DAC, 2024)

MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. - Vasudev Gohil; Rahul Kande; Chen Chen 125; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (DATE, 2024)

Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing. - Mohamadreza Rostami; Marco Chilese; Shaza Zeitouni; Rahul Kande; Jeyavijayan Rajendran; Ahmad-Reza Sadeghi (DATE, 2024)

Performance Analysis of Zero-Knowledge Proofs. - Saichand Samudrala; Jiawen Wu; Chen Chen 125; Haoxuan Shan; Jonathan Ku; Yiran Chen 001; Jeyavijayan Rajendran (IISWC, 2024)

WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors. - Pallavi Borkar; Chen Chen 125; Mohamadreza Rostami; Nikhilesh Singh; Rahul Kande; Ahmad-Reza Sadeghi; Chester Rebeiro; Jeyavijayan Rajendran (USENIX Security Symposium, 2024)

AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning. - Vasudev Gohil; Satwik Patnaik; Dileep Kalathil; Jeyavijayan Rajendran (USENIX Security Symposium, 2024)

LLMs for Hardware Security: Boon or Bane? - Rahul Kande; Vasudev Gohil; Matthew DeLorenzo; Chen Chen 125; Jeyavijayan Rajendran (VTS, 2024)

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS. - Matthew DeLorenzo; Animesh Basak Chowdhury; Vasudev Gohil; Shailja Thakur; Ramesh Karri; Siddharth Garg; Jeyavijayan Rajendran (CoRR, 2024)

CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation. - Matthew DeLorenzo; Vasudev Gohil; Jeyavijayan Rajendran (CoRR, 2024)

Fuzzerfly Effect: Hardware Fuzzing for Memory Safety. - Mohamadreza Rostami; Chen Chen 125; Rahul Kande; Huimin Li 004; Jeyavijayan Rajendran; Ahmad-Reza Sadeghi (IEEE Secur. Priv., 2024)

(Security) Assertions by Large Language Models. - Rahul Kande; Hammond Pearce; Benjamin Tan 001; Brendan Dolan-Gavitt; Shailja Thakur; Ramesh Karri; Jeyavijayan Rajendran (IEEE Trans. Inf. Forensics Secur., 2024)

DETERRENT: Detecting Trojans Using Reinforcement Learning. - Vasudev Gohil; Satwik Patnaik; Hao Guo; Dileep Kalathil; Jeyavijayan Rajendran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation. - Zhaokun Han; Aneesh Dixit; Satwik Patnaik; Jeyavijayan Rajendran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Enhancing Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-Dependent Industrial Infrastructures. - Peng-Hao Huang; Jaewon Kim; P. R. Kumar 001; Jeyavijayan Rajendran; Prasad Enjeti (IEEE Internet Things J., 2024)

Watermarking LLMs - Challenges and Opportunities in Electronic Design Automation. - Matthew DeLorenzo; Phat Tieu; Chen Chen 125; Vasudev Gohil; Jeyavijayan Rajendran (COINS, 2025)

LLMPirate: LLMs for Black-box Hardware IP Piracy. - Vasudev Gohil; Matthew DeLorenzo; Veera Vishwa Achuta Sai Venkat Nallam; Joey See; Jeyavijayan Rajendran (NDSS, 2025)

Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs. - Sam Bush; Matthew DeLorenzo; Phat Tieu; Jeyavijayan Rajendran (CoRR, 2025)

Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization. - Fenghua Wu; Evan Pan; Rahul Kande; Michael Quinn; Aakash Tyagi; David Kebo Houngninou; Jeyavijayan Rajendran; Jiang Hu (CoRR, 2025)

Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design. - Matthew DeLorenzo; Kevin Tieu; Prithwish Jana; Piyush Jha; Dileep Kalathil; Vijay Ganesh 001; Jeyavijayan Rajendran (CoRR, 2025)