A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. - Pei-Ci Wu; Jhih-Rong Gao; Ting-Chi Wang (ASP-DAC, 2007)

A new global router for modern designs. - Jhih-Rong Gao; Pei-Ci Wu; Ting-Chi Wang (ASP-DAC, 2008)

NTHU-Route 2.0: A Robust Global Router for Modern Designs. - Yen-Jung Chang; Yu-Ting Lee; Jhih-Rong Gao; Pei-Ci Wu; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection. - Duo Ding; Jhih-Rong Gao; Kun Yuan 002; David Z. Pan (DAC, 2011)

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). - Bei Yu 001; Jhih-Rong Gao; Duo Ding; Yongchan Ban; Jae-Seok Yang; Kun Yuan 002; Minsik Cho; David Z. Pan (ICCAD, 2012)

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. - Jhih-Rong Gao; David Z. Pan (ISPD, 2012)

VLSI CAD for emerging nanolithography. - David Z. Pan; Jhih-Rong Gao; Bei Yu 001 (VLSI-DAT, 2012)

Lithography hotspot detection and mitigation in nanometer VLSI. - Jhih-Rong Gao; Bei Yu 001; Duo Ding; David Z. Pan (ASICON, 2013)

L-shape based layout fracturing for e-beam lithography. - Bei Yu 001; Jhih-Rong Gao; David Z. Pan (ASP-DAC, 2013)

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. - Bei Yu 001; Kun Yuan 002; Jhih-Rong Gao; David Z. Pan (DAC, 2013)

Methodology for standard cell compliance and detailed placement for triple patterning lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; David Z. Pan (ICCAD, 2013)

Design for Manufacturing With Emerging Nanolithography. - David Z. Pan; Bei Yu 001; Jhih-Rong Gao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Self-aligned double patterning layout decomposition with complementary e-beam lithography. - Jhih-Rong Gao; Bei Yu 001; David Z. Pan (ASP-DAC, 2014)

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction. - Jhih-Rong Gao; Xiaoqing Xu; Bei Yu 001; David Z. Pan (DAC, 2014)

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement. - Jhih-Rong Gao; Bei Yu 001; Ru Huang 001; David Z. Pan (CoRR, 2014)

Lithography Hotspot Detection and Mitigation in Nanometer VLSI. - Jhih-Rong Gao; Bei Yu 001; David Z. Pan (CoRR, 2014)

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting. - Bei Yu 001; Jhih-Rong Gao; David Z. Pan (CoRR, 2014)

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). - Bei Yu 001; Subhendu Roy; Jhih-Rong Gao; David Z. Pan (CoRR, 2014)

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design. - Jiaojiao Ou; Bei Yu 001; Jhih-Rong Gao; David Z. Pan; Moshe Preil; Azat Latypov (ACM Great Lakes Symposium on VLSI, 2015)

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Yibo Lin; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. - Xiaoqing Xu; Bei Yu 001; Jhih-Rong Gao; Che-Lun Hsu; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2016)

EBL Overlapping Aware Stencil Planning for MCC System. - Bei Yu 001; Kun Yuan 002; Jhih-Rong Gao; Shiyan Hu 001; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2016)

A unified framework for simultaneous layout decomposition and mask optimization. - Yuzhe Ma; Jhih-Rong Gao; Jian Kuang 001; Jin Miao; Bei Yu 001 (ICCAD, 2017)

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. - Yibo Lin; Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Natarajan Viswanathan; Wen-Hao Liu 001; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization. - Yuzhe Ma; Wei Zhong; Shuxiang Hu; Jhih-Rong Gao; Jian Kuang 001; Jin Miao; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)