13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. - Yen-Huei Chen; Wei-Min Chan; Wei-Cheng Wu; Hung-Jen Liao; Kuo-Hua Pan; Jhon-Jhy Liaw; Tang-Hsuan Chung; Quincy Li; George H. Chang; Chih-Yung Lin; Mu-Chi Chiang; Shien-Yang Wu; et al. (ISSCC, 2014)

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. - Hidehiro Fujiwara; Li-Wen Wang; Yen-Huei Chen; Kao-Cheng Lin; Dar Sun; Shin-Rung Wu; Jhon-Jhy Liaw; Chih-Yung Lin; Mu-Chi Chiang; Hung-Jen Liao; Shien-Yang Wu; Jonathan Chang (ISSCC, 2015)

A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. - Yen-Huei Chen; Wei-Min Chan; Wei-Cheng Wu; Hung-Jen Liao; Kuo-Hua Pan; Jhon-Jhy Liaw; Tang-Hsuan Chung; Quincy Li; Chih-Yung Lin; Mu-Chi Chiang; Shien-Yang Wu; Jonathan Chang (IEEE J. Solid State Circuits, 2015)

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. - Yen-Huei Chen; Kao-Cheng Lin; Ching-Wei Wu; Wei-Min Chan; Jhon-Jhy Liaw; Hung-Jen Liao; Jonathan Chang (VLSI Circuits, 2016)

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Sahil Preet Singh; Hank Cheng; Hidehiro Fujiwara; Jih-Yu Lin; Kao-Cheng Lin; John Hung; Robin Lee; Hung-Jen Liao; Jhon-Jhy Liaw; et al. (ISSCC, 2017)

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. - Hidehiro Fujiwara; Chih-Yu Lin; Hsien-Yu Pan; Cheng-Han Lin; Po-Yi Huang; Kao-Cheng Lin; Jhon-Jhy Liaw; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2019)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Michael Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. - Hidehiro Fujiwara; Wei-Chang Zhao; Kinshuk Khare; Yi-Hsin Nien; Chih-Yu Lin; Cheng-Han Lin; Shan-Ru Liao; Kenta Torigoe; Shirleen Xia; Yuichiro Ishii; Yao-Yi Lin; Jhon-Jhy Liaw; et al. (ISSCC, 2025)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Yumito Aoyagi; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)