ESD-Immunity Impact of HV pLDMOS with Drain-side Embedded Horizontal P-type Schottky Modulations. - Shi-Zhe Hong; Shen-Li Chen; Tien-Yu Lan; Yu-Jie Zhou; Zhi-Wei Liu; Jhong-Yi Lai (ICCE-TW, 2021)

Holding-voltage Improvement of UHV Circular nLDMOS Transistors by the Drain-side SCR Engineering. - Tien-Yu Lan; Shen-Li Chen; Yu-Jie Zhou; Shi-Zhe Hong; Jhong-Yi Lai; Zhi-Wei Liu (ICCE-TW, 2021)

ESD Capability Analysis of High-voltage nLDMOSs by the Bulk Terminal Modulation. - Jhong-Yi Lai; Shen-Li Chen; Zhi-Wei Liu; Xing-Chen Mai; Yu-Jie Chung (ICCE-TW, 2022)

An Investigation of ESD-Enhancement by the Drain-side Embedded SCR Area Modulation for HV pLDMOSs. - Zhi-Wei Liu; Shen-Li Chen; Jhong-Yi Lai; Xing-Chen Mai; Yu-Jie Chung (ICCE-TW, 2022)

ESD-capability Study of High-voltage nLDMOSs with out the Drift Region DPW Effect. - Xiu-Yuan Yang; Xing-Chen Mai; Shen-Li Chen; Yu-Jie Chung; Jhong-Yi Lai; Ting-En Lin (ICCE-Taiwan, 2023)